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| 型號： | AD9445BSVZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 125MSPS 100-TQFP |
| 設計資源： | Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046) Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110) |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.6W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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AD9445
Rev. 0 | Page 14 of 40
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode
Pin No.
Mnemonic
Description
1
DCS MODE
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable
DCS (recommended); DCS = high (AVDD1) to disable DCS.
2, 49 to 62, 65 to 66, 69 to 71
DNC
Do Not Connect. These pins should float.
3
OUTPUT
MODE
CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4
DFS
Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.
5
LVDS_BIAS
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, 38,
43 to 45, 92 to 97
AVDD1
3.3 V (±5%) Analog Supply.
7
SENSE
Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1 for
external reference.
8
VREF
1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 μF and 10 μF capacitors.
9, 21, 24, 39, 42, 46, 91, 98,
99, Exposed Heat Sink
AGND
Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.
10
REFT
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB
(Pin 14) with 0.1 μF and 10 μF capacitors.
11
REFB
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 13) with 0.1 μF and 10 μF capacitors.
12 to 17, 25 to 31, 35, 37
AVDD2
5.0 V Analog Supply (±5%).
22
VIN+
Analog Input—True.
23
VIN
Analog Input—Complement.
40
CLK+
Clock Input—True.
41
CLK
Clock Input—Complement.
47, 63, 75, 87
DRGND
Digital Output Ground.
48, 64, 76, 88
DRVDD
3.3 V Digital Output Supply (3.0 V to 3.6 V).
67
DCO
Data Clock Output—Complement.
68
DCO+
Data Clock Output—True.
72
D0 (LSB)
D0 True Output Bit (CMOS levels).
73
D1
D1 True Output Bit.
74
D2
D2 True Output Bit.
77
D3
D3 True Output Bit.
78
D4
D4 True Output Bit.
79
D5
D5 True Output Bit.
80
D6
D6 True Output Bit.
81
D7
D7 True Output Bit.
82
D8
D8 True Output Bit.
83
D9
D9 True Output Bit.
84
D10
D10 True Output Bit.
85
D11
D11 True Output Bit.
86
D12
D12 True Output Bit.
89
D13 (MSB)
D13 True Output Bit.
90
OR
Out-of-Range True Output Bit.
100
RF ENABLE
RF ENABLE CMOS-compatible Control Pin. Optimizes the configuration of the analog front end.
Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input
frequencies <210 MHz for 125 MSPS speed grade and <230 MHz for the 105 MSPS speed grade.
For applications with analog inputs >225 MHz for the 125 MSPS speed grade and >230 MHz
for the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR.
Power dissipation from AVDD2 increases by 150 mW to 200 mW.
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