參數(shù)資料
型號(hào): AD9445BSVZ-105
廠商: Analog Devices Inc
文件頁(yè)數(shù): 4/40頁(yè)
文件大小: 0K
描述: IC ADC 14BIT 105MSPS 100-TQFP
設(shè)計(jì)資源: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002)
Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046)
Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110)
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.4W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤(pán)
輸入數(shù)目和類(lèi)型: 1 個(gè)差分,單極
AD9445
Rev. 0 | Page 12 of 40
Pin No.
Mnemonic
Description
83
D12
D12 Complement Output Bit.
84
D12+
D12 True Output Bit.
85
D13
D13 Complement Output Bit.
86
D13+ (MSB)
D13 True Output Bit.
89
OR
Out-of-Range Complement Output Bit.
90
OR+
Out-of-Range True Output Bit.
100
RF ENABLE
RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of
the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies <210 MHz for 125 MSPS
speed grade and <230 MHz for the 105 MSPS speed grade. For applications with analog
inputs >225 MHz for the 125 MSPS speed grade and >230 MHz for the 105 MSPS speed
grade, this pin should be connected to AVDD1 for optimum SFDR performance. Power
dissipation from AVDD2 increases by 150 mW to 200 mW.
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