參數(shù)資料
型號(hào)： AD9284BCPZRL7-250
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 8BIT 250MSPS 1.8V 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 8
采樣率（每秒）： 250M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 330mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)差分，雙極
配用： AD9284-250EBZ-ND - BOARD EVAL FOR AD9284
Data Sheet
AD9284
Rev. A | Page 13 of 24
THEORY OF OPERATION
The AD9284 is a pipeline-type converter. The input buffers are
differential, and both sets of inputs are internally biased. This
allows the use of ac or dc input modes. A sample-and-hold
amplifier is incorporated into the first stage of the multistage
pipeline converter core. The output staging block aligns the
data, carries out error correction for the pipeline stages, and
feeds that data to the output buffers. The two ADC channels
are sampled simultaneously through a single encoding clock.
All user-selected options are programmed through dedicated
digital input pins or a serial port interface (SPI).
ADC ARCHITECTURE
Each channel of the AD9284 consists of a differential input
buffer followed by a sample-and-hold amplifier (SHA). The
SHA is followed by a pipeline switched-capacitor ADC. The
quantized outputs from each stage are combined into a final
8-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, whereas the remaining stages operate on preceding
samples.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output
staging block aligns the data, carries out error correction, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
enter a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog inputs of the AD9284 are differentially buffered.
For best dynamic performance, the source impedances driving
VIN+A, VIN+B, VINA, and VINB should be matched such
that common-mode settling errors are symmetrical. The analog
inputs are optimized to provide superior wideband performance
and must be driven differentially. SNR and SINAD performance
degrades significantly if the analog inputs are driven with a single-
ended signal.
A wideband transformer, such as Mini-Circuits ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to
a nominal 1.4 V.
Differential Input Configurations
Optimum performance is achieved when driving the AD9284
in a differential input configuration. For baseband applications,
the ADA4937-1 differential driver provides excellent performance
and a flexible interface to the ADC (see Figure 19). The output
common-mode voltage of the AD9284 is easily set to 1.4 V, and
the driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
–
+
200
227.4
61.9
ADA4937-1
1.2V p-p
0.1F
200
4.7pF
33
VIN
+
–
AD9284
VCM
09085-
025
Figure 19. Differential Input Configuration Using the ADA4937-1
The AD9284 can also be driven passively with a differential
transformer-coupled input (see Figure 20). To bias the analog
input, the VCM voltage can be connected to the center tap of
the secondary winding of the transformer.
49.9
1.2V p-p
4.7pF
0.1F
33
VIN
+
–
AD9284
VCM
09085-
026
Figure 20. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies below
a few megahertz (MHz). Excessive signal power can also cause
core saturation, which leads to distortion.
VOLTAGE REFERENCE
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.2 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of SPI control. It can also be driven externally with
an off-chip stable reference. See the Memory Map Register
Descriptions section for more details.
RBIAS
The AD9284 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resistor, which is used to set
the master current reference of the ADC core, should have a 1%
tolerance.
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