參數(shù)資料
型號(hào)： AD9280ARSZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC CMOS 8BIT 32MSPS 28-SSOP
產(chǎn)品變化通告： AD9280 Pin Configuration Description Change 21/Apr/2010
標(biāo)準(zhǔn)包裝： 47
位數(shù)： 8
采樣率（每秒）： 32M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 110mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
產(chǎn)品目錄頁(yè)面： 780 (CN2011-ZH PDF)
AD9280
–6–
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
Typical Characterization Curves
CODE OFFSET
1.0
0.5
–1.0
0
240
32
DNL
64
96
128
160
192
224
0
–0.5
Figure 3. Typical DNL
CODE OFFSET
1.0
INL
0.5
–1.0
0
240
32
64
96
128
160
192
224
0
–0.5
Figure 4. Typical INL
Offset Error
The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi-
tion from that point.
Gain Error
The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full
scale. Gain error is the deviation of the actual difference be-
tween first and last code transitions and the ideal difference
between the first and last code transitions.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising edge.
INPUT FREQUENCY – Hz
60
55
20
1.00E+05
1.00E+08
1.00E+06
1.00E+07
50
45
25
40
35
30
SNR–
dB
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
Figure 5. SNR vs. Input Frequency
60
55
20
1.00E+05
1.00E+08
1.00E+06
SINAD
–
dB
1.00E+07
50
45
25
40
35
30
INPUT FREQUENCY – Hz
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
Figure 6. SINAD vs. Input Frequency
(AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)
REV. E
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