參數(shù)資料
型號(hào)： AD9276BSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/48頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT LNA/VGA/AAF 100TQFP
標(biāo)準(zhǔn)包裝： 1
類型： AAF，ADC，解調(diào)器，LNA，VGA
分辨率（位）： 12 b
采樣率（每秒）： 10M ~ 80M
數(shù)據(jù)接口： 串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 1.8V，3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
AD9276
Rev. 0 | Page 35 of 48
By asserting the PDWN pin high, the AD9276 is placed into
power-down mode. In this state, the device typically dissipates
5 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. The AD9276 returns to normal
operating mode when the PDWN pin is pulled low. This pin
is both 1.8 V and 3.3 V tolerant.
By asserting the STBY pin high, the AD9276 is placed into a
standby mode. In this state, the device typically dissipates 175 mW.
During standby, the entire part is powered down except for the
internal references. The LVDS output drivers are placed into a
high impedance state. This mode is well suited for applications
that require power savings because it allows the device to be
powered down when not in use and then quickly powered up.
The time to power the device back up is also greatly reduced.
The AD9276 returns to normal operating mode when the STBY
pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on VREF are discharged
when entering power-down mode and must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in the power-down mode: shorter cycles
result in proportionally shorter wake-up times. To restore the
device to full operation, approximately 0.5 ms is required when
using the recommended 1 μF and 0.1 μF decoupling capacitors
on the VREF pin and the 0.01 μF decoupling capacitors on the
GAIN± pins. Most of this time is dependent on the gain decou-
pling: higher value decoupling capacitors on the GAIN± pins
result in longer wake-up times.
A number of other power-down options are available when
using the SPI port interface. The user can individually power
down each channel or put the entire device into standby mode.
This allows the user to keep the internal PLL powered up when
fast wake-up times are required. The wake-up time is slightly
dependent on gain. To achieve a 1 μs wake-up time when the
device is in standby mode, 0.8 V must be applied to the GAIN±
pins. See Table 18 for more details on using these features.
DIGITAL OUTPUTS AND TIMING
The AD9276 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to
a low power, reduced signal option similar to the IEEE 1596.3
standard via the SPI, using Register 0x14, Bit 6. This LVDS
standard can further reduce the overall power dissipation of
the device by approximately 36 mW.
The LVDS driver current is derived on chip and sets the output
current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing at the receiver.
The AD9276 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point network topologies are recommended with
a 100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths. An example of the FCO, DCO, and data stream with
proper trace length and position is shown in Figure 72.
08
18
0-
0
66
CH1 500mV/DIV = DCO
CH2 500mV/DIV = DATA
CH3 500mV/DIV = FCO
5.0ns/DIV
Figure 72. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on regular FR-4 material
is shown in Figure 73. Figure 74 shows an example of the trace
lengths exceeding 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position; therefore,
the user must determine whether the waveforms meet the timing
budget of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the
internal termination (and therefore increase the current) of all
eight outputs in order to drive longer trace lengths (see Figure 75).
Even though this produces sharper rise and fall times on the
data edges, is less prone to bit errors, and improves frequency
distribution (see Figure 75), the power dissipation of the
DRVDD supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, the user can double the
drive strength by setting Bit 0 in Register 0x15. Note that this
feature cannot be used with Bits[5:4] in Register 0x15 because
these bits take precedence over this feature. See Table 18 for
more details.
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