參數(shù)資料
型號： AD9269BCPZ-20
廠商： Analog Devices Inc
文件頁數(shù)： 27/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT SER 2CH 64LFCSP
特色產(chǎn)品： AD9269/65 Low-Power, High-Speed 16-Bit, 1.8V ADCs
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 102mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極
AD9269
Rev. 0 | Page 33 of 40
Addr.
(Hex)
Register
Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Comments
0x0D
Test mode (local)
User test mode
(local)
00 = single
01 = alternate
10 = single once
11 = alternate
once
Reset PN
long gen
Reset PN
short
gen
Output test mode [3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
0x00
When set, the test
data is placed on
the output pins
in place of
normal data
0x0E
BIST enable
Open
BIST init
Open
BIST
enable
0x00
When Bit 0 is set,
the BIST function
is initiated
0x10
Offset adjust
(local)
8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to 128 (twos complement format)
0x00
Device offset trim
0x14
Output mode
00 = 3.3 V CMOS
10 = 1.8 V CMOS
Output mux
enable
(interleaved)
Output
disable
(OEB)
(local)
Open
Output
invert
(local)
00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
(local)
0x00
Configures the
outputs and the
format of the data
0x15
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V DCO drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
0x22
Determines
CMOS output
drive strength
properties
0x16
DCO
output
polarity
0 =
normal
1 =
inverted
(local)
Open
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
0x00
On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock;
internal latching
is unaffected
0x17
OUTPUT_DELAY
Enable
DCO
delay
Open
Enable
data
delay
Open
DCO/data delay, Bits[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
0x00
This sets the fine
output delay of
the output clock
but does not
change internal
timing
0x19
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-
Defined
Pattern 1, LSB
0x1A
B15
B14
B13
B12
B11
B10
B9
B8
0x00
User-defined
Pattern 1, MSB
0x1B
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-
Defined
Pattern 2, LSB
0x1C
B15
B14
B13
B12
B11
B10
B9
B8
0x00
User-
Defined
Pattern 2, MSB
0x24
Open
B0
0x00
Least significant
byte of MISR;
read only
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