- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10522 > AD9266BCPZ-20 (Analog Devices Inc)IC ADC 16BIT 20MSPS 32LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9266BCPZ-20 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/32頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 20MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 63mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Data Sheet
AD9266
Rev. A | Page 21 of 32
Input Clock Divider
The AD9266 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
Optimum performance can be obtained by enabling the internal
duty cycle stabilizer (DCS) when using divide ratios other than
1, 2, or 4.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9266 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9266. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 51.
80
79
78
77
76
70
71
72
73
74
75
30
35
40
45
50
55
60
65
70
S
NR
(
d
BF
S
)
POSITIVE DUTY CYCLE (%)
DCS OFF
DCS ON
08678-
064
Figure 51. SNR vs. DCS On/Off
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 s to 5 s
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR from the low frequency
SNR (SNRLF) at a given input frequency (fINPUT) due to jitter
(tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
)
10
/
(
LF
SNR
]
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 52.
80
75
70
65
60
55
50
45
1
10
100
1k
FREQUENCY (MHz)
S
NR
(
d
BF
S
)
0.5ps
0.2ps
0.05ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
08678-
022
Figure 52. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal when
aperture jitter may affect the dynamic range of the AD9266. To
avoid modulating the clock signal with digital noise, keep power
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
For more information, see the AN-501 Application Note and
the AN-756 Application Note available at www.analog.com.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UTS6JC1419P | CONN PLUG CABLE 19X1.0 MALE |
| AD677JNZ | IC ADC 16BIT SAMPLING 16-DIP |
| UP050B221K-NAC | CAP CER 220PF 50V 10% AXIAL |
| UTS6JC147S | CONN PLUG CABLE 7X1.6 FEMALE |
| AD9628BCPZ-105 | IC ADC DUAL 12BIT 64-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9266BCPZ-40 | 制造商:Analog Devices 功能描述:16 BIT, 40 MSPS 1.8V SINGLE ADC - Trays 制造商:Analog Devices 功能描述:IC ADC 16BIT 40MSPS 32LFCSP 制造商:Analog Devices Inc. 功能描述:Analog to Digital Converters - ADC 16 Bit 40 MSPS 1.8V Single ADC 制造商:Analog Devices 功能描述:CONVERTER - ADC |
| AD9266BCPZ-65 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 65 MSPS 1.8V Single ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9266BCPZ-80 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 80 MSPS 1.8V Single ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9266BCPZRL7-20 | 功能描述:IC ADC 16BIT 20MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9266BCPZRL7-40 | 制造商:Analog Devices 功能描述:16 BIT, 40 MSPS 1.8V SINGLE ADC - Tape and Reel 制造商:Analog Devices 功能描述:IC ADC 16BIT 40MSPS 32LFCSP 制造商:Analog Devices Inc. 功能描述:Analog to Digital Converters - ADC 16 Bit 40 MSPS 1.8V Single ADC 制造商:Analog Devices 功能描述:CONVERTER - ADC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。