參數(shù)資料
型號(hào)： AD9257-65EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/40頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9257
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 8
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 55mW @ 65MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9257
已供物品： 板
Data Sheet
AD9257
Rev. A | Page 21 of 40
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 53. The AD9510/
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
Input Clock Divider
The AD9257 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
The AD9257 clock divider can be synchronized using the
external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a vari-
ety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9257 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the per-
formance of the AD9257. Noise and distortion performance are
nearly flat for a wide range of duty cycles with the DCS on.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 s to 5 s
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
10
0
0.1F
240
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
10206-
051
Figure 52. Differential PECL Sample Clock (Up to 520 MHz)
10
0
0.1F
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
10206-
052
Figure 53. Differential LVDS Sample Clock (Up to 520 MHz)
OPTIONAL
100
0.1F
501
1
50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
10206-
053
Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
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