- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17026 > AD9253-125EBZ (Analog Devices Inc)BOARD EVAL FOR AD9253-125 PDF資料下載
參數(shù)資料
| 型號： | AD9253-125EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9253-125 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 4 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | LVDS，串行，SPI? |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標準）： | 110mW @ 25MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9253 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
AD9253
Data Sheet
Rev. 0 | Page 24 of 40
3.0
If the internal reference of the AD9253 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 60 shows
how the internal reference voltage is affected by loading.
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
0
2.5
2.0
1.5
1.0
0.5
V
RE
F
E
R
RO
R
(
%
)
LOAD CURRENT (mA)
1006
5-
061
INTERNAL VREF = 1V
Figure 60. VREF Error vs. Load Current
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 61 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
4
–8
–40
85
V
RE
F
E
RRO
R
(
m
V
)
TEMPERATURE (°C)
10
065
-06
2
–6
–4
–2
0
2
–15
10
35
60
Figure 61. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 54). The internal buffer generates the
positive and negative full-scale references for the ADC core. There-
fore, the external reference must be limited to a maximum of 1.0 V.
It is not recommended to leave the SENSE pin floating.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9253 sample clock
inputs, CLK+ and CLK, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK pins via a
transformer or capacitors. These pins are biased internally
(see Figure 48) and require no external bias.
Clock Input Options
The AD9253 has a flexible clock input structure. The clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
ing the AD9253 (at clock rates up to 1 GHz prior to internal CLK
divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9253 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9253 while
preserving the fast rise and fall times of the signal that are critical
to achieving low jitter performance. However, the diode
capacitance comes into play at frequencies above 500 MHz. Care
must be taken in choosing the appropriate signal limiting diode.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
1
006
5-
06
4
Figure 62. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
CLOCK
INPUT
0.1F
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
1
006
5-
065
Figure 63. Balun-Coupled Differential Clock (Up to 1 GHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
相關PDF資料 |
PDF描述 |
|---|---|
| GCM15DRYF | CONN EDGECARD 30POS DIP .156 SLD |
| VE-2WX-EY | CONVERTER MOD DC/DC 5.2V 50W |
| STD21W-G | WIRE & CABLE MARKERS |
| STD21W-U | WIRE & CABLE MARKERS |
| 381LX221M250J012 | CAP ALUM 220UF 250V 20% SNAP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9253BCPZ-105 | 功能描述:IC ADC 14BIT SRL 105MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9253BCPZ-125 | 功能描述:IC ADC 14BIT SRL 125MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD9253BCPZ-80 | 功能描述:IC ADC 14BIT SRL 80MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9253BCPZRL7-105 | 功能描述:模數(shù)轉換器 - ADC 14 Bit 105Msps Quad ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD9253BCPZRL7-125 | 功能描述:模數(shù)轉換器 - ADC 14 Bit 125Msps Quad ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
發(fā)布緊急采購，3分鐘左右您將得到回復。