參數(shù)資料
型號: AD9252ABCPZ-50
廠商: Analog Devices Inc
文件頁數(shù): 23/52頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SRL 50MSPS 64LFCSP
標(biāo)準包裝: 1
位數(shù): 14
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 773mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
輸入數(shù)目和類型: 16 個單端,單極;8 個差分,單極
Data Sheet
AD9252
Rev. E | Page 3 of 52
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Table 1.
AD9252-50
Parameter1
Temperature
Min
Typ
Max
Unit
RESOLUTION
14
Bits
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
Full
±1
±8
mV
Offset Matching
Full
±3
±8
mV
Gain Error
Full
±1.5
±2.5
% FS
Gain Matching
Full
±0.3
±0.7
% FS
Differential Nonlinearity (DNL)
Full
±0.4
±1
LSB
Integral Nonlinearity (INL)
Full
±1.5
±4
LSB
TEMPERATURE DRIFT
Offset Error
Full
±2
ppm/°C
Gain Error
Full
±17
ppm/°C
Reference Voltage (1 V Mode)
Full
±21
ppm/°C
REFERENCE
Output Voltage Error (VREF = 1 V)
Full
±2
±30
mV
Load Regulation @ 1.0 mA (VREF = 1 V)
Full
3
mV
Input Resistance
Full
6
k
ANALOG INPUTS
Differential Input Voltage Range (VREF = 1 V)
Full
2
V p-p
Common-Mode Voltage
Full
AVDD/2
V
Differential Input Capacitance
Full
7
pF
Analog Bandwidth, Full Power
Full
325
MHz
POWER SUPPLY
AVDD
Full
1.7
1.8
1.9
V
DRVDD
Full
1.7
1.8
1.9
V
IAVDD
Full
360
373.4
mA
IDRVDD
Full
55.5
58
mA
Total Power Dissipation (Including Output Drivers)
Full
748
773
mW
Power-Down Dissipation
Full
2
11
mW
Standby Dissipation2
Full
89
mW
CROSSTALK
AIN = 0.5 dBFS
Full
90
dB
Overrange3
Full
90
dB
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Can be controlled via the SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.
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