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參數(shù)資料
| 型號： | AD9252-50EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/52頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9252 |
| 設計資源： | AD9212/22/52 Gerber Files |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 8 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標準）： | 748mW @ 50MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9252-50 |
| 已供物品： | 板 |
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Data Sheet
AD9252
Rev. E | Page 25 of 52
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored. This pin is both 1.8 V and
3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
that is nominally equal to 10.0 k between the RBIAS pin and
ground. The resistor current is derived on chip and sets the
AVDD current of the ADC to a nominal 360 mA at 50 MSPS.
Therefore, it is imperative that at least a 1% tolerance on this
resistor be used to achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the
AD9252. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input
span of 2 V p-p. VREF is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
improve accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low-ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9252. The recommended capacitor values and
configurations for the AD9252 reference pin are shown in
Table 13. Reference Settings
Selected
Mode
SENSE
Voltage
Resulting
VREF (V)
Resulting
Differential
Span (V p-p)
External
Reference
AVDD
N/A
2 × external
reference
Internal,
2 V p-p FSR
AGND to 0.2 V
1.0
2.0
Internal Reference Operation
A comparator within the AD9252 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 51), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9252 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 53
depicts how the internal reference voltage is affected by loading.
1F
0.1F
VREF
SENSE
0.5V
REFT
0.1F
4.7F
0.1F
REFB
SELECT
LOGIC
ADC
CORE
+
VIN – x
VIN + x
06296-
031
Figure 51. Internal Reference Configuration
1F1
0.1F1
VREF
SENSE
AVDD
0.5V
REFT
0.1F
4.7F
0.1F
REFB
SELECT
LOGIC
ADC
CORE
+
VIN – x
VIN + x
EXTERNAL
REFERENCE
1OPTIONAL.
06296-
032
Figure 52. External Reference Operation
0
1.0
0.5
2.0
1.5
3.0
2.5
3.5
V
RE
F
E
RRO
R
(
%)
CURRENT LOAD (mA)
06296-
061
–30
–5
–10
–15
–20
–25
5
0
Figure 53. VREF Accuracy vs. Load
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| AD9252ABCPZRL7-50 | 功能描述:IC ADC 14BIT SRL 50MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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