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| 型號： | AD9248BCPZRL-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT DUAL 65MSPS 64LFCSP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 600mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9248
Rev. B | Page 10 of 48
Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4, 13, 16
AGND
Analog Ground.
2
VIN+_A
Analog Input Pin (+) for Channel A.
3
VIN_A
Analog Input Pin () for Channel A.
5, 12, 17, 64
AVDD
Analog Power Supply.
6
REFT_A
Differential Reference (+) for Channel A.
7
REFB_A
Differential Reference () for Channel A.
8
VREF
Voltage Reference Input/Output.
9
SENSE
Reference Mode Selection.
10
REFB_B
Differential Reference () for Channel B.
11
REFT_B
Differential Reference (+) for Channel B.
14
VIN_B
Analog Input Pin () for Channel B.
15
VIN+_B
Analog Input Pin (+) for Channel B.
18
CLK_B
Clock Input Pin for Channel B.
19
DCS
Enable Duty Cycle Stabilizer (DCS) Mode.
20
DFS
Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement).
21
PDWN_B
Power-Down Function Selection for Channel B.
Logic 0 enables Channel B. Logic 1 powers down Channel B (outputs static, not High-Z).
22
OEB_B
Output Enable Pin for Channel B.
Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z.
23 to 27,
30 to 38
D0_B (LSB) to
D13_B (MSB)
Channel B Data Output Bits.
28, 40, 53
DRGND
Digital Output Ground.
29, 41, 52
DRVDD
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF capacitor.
39
OTR_B
Out-of-Range Indicator for Channel B.
42 to 51,
54 to 57
D0_A (LSB) to
D13_A (MSB)
Channel A Data Output Bits.
58
OTR_A
Out-of-Range Indicator for Channel A.
59
OEB_A
Output Enable Pin for Channel A.
Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z.
60
PDWN_A
Power-Down Function Selection for Channel A.
Logic 0 enables Channel A. Logic 1 powers down Channel A (outputs static, not High-Z).
61
MUX_SELECT
Data Multiplexed Mode.
(See Data Format section for how to enable; high setting disables output data multiplexed mode.)
62
SHARED_REF
Shared Reference Control Pin (Low for Independent Reference Mode, High for Shared Reference Mode).
63
CLK_A
Clock Input Pin for Channel A.
EP
For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.
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