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參數資料
| 型號： | AD9248BCPZRL-20 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 11/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT DUAL 20MSPS 64LFCSP |
| 標準包裝： | 2,500 |
| 位數： | 14 |
| 采樣率（每秒）： | 20M |
| 數據接口： | 并聯(lián) |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 180mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9248
Rev. B | Page 19 of 48
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9248 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
DIGITAL OUTPUTS
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
The AD9248 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
where N is the number of bits changing, and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9248 can be placed into standby mode
independently by asserting the PDWN_A or PDWN_B pins.
The data format can be selected for either offset binary or twos
complement. See the Data Format section for more information.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 1 mW for the ADC.
Note that if DCS is enabled, it is mandatory to disable the clock
of an independently powered-down channel. Otherwise,
significant distortion results on the active channel. If the clock
inputs remain active while in total standby mode, typical power
dissipation of 12 mW results.
TIMING
The AD9248 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propa-
gation delay (tPD) after the rising edge of the clock signal. Refer
to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the AD9248
using the DCS pin. This provides a stable 50% duty cycle to
internal circuits.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B =
HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time is directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down. Typically, it takes approximately
5 ms to restore full operation with fully discharged 0.1 μF and
10 μF decoupling capacitors on REFT and REFB.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9248.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9248
is 1 MSPS. At clock rates below 1 MSPS, dynamic performance
may degrade.
B–8
A–7
B–7
A–6
B–6
A–5
B–5
A–4
B–4
A–3
B–3
A–2
B–2
A–1
B–1
A0
B0
A1
A–1
A0
A1
A2
A3
A4
A5
A6
A7
A8
B–1
B0
B1
B2
B3
B4
B5
B6
B7
B8
ANALOG INPUT
ADC A
ANALOG INPUT
ADC B
CLK_A = CLK_B =
MUX_SELECT
D0_A TO
D11_A
tPD
04446-033
Figure 34. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9248BCPZRL-40 | 功能描述:IC ADC 14BIT DUAL 40MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD9248BCPZRL-65 | 功能描述:IC ADC 14BIT DUAL 65MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD9248BCPZRL7-20 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BCPZRL7-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BCPZRL7-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
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