參數(shù)資料
型號(hào): AD9245BCPZRL7-80
廠商: Analog Devices Inc
文件頁數(shù): 31/32頁
文件大小: 0K
描述: IC ADC 14BIT SGL 80MSPS 32LFCSP
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 414mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
AD9245
Data Sheet
Rev. E | Page 8 of 32
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 6.
Parameter
AD9245BCP-20
AD9245BCP-40
AD9245BCP-65
AD9245BCP-80
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
20
40
65
80
MSPS
Minimum Conversion Rate
1
MSPS
CLK Period
50.0
25.0
15.4
12.5
ns
CLK Pulse Width High1
15.0
8.8
6.2
4.6
ns
CLK Pulse Width Low1
15.0
8.8
6.2
4.6
ns
DATA OUTPUT PARAMETERS
Output Delay2 (tPD)
3.5
4.2
ns
Pipeline Delay (Latency)
7
Cycles
Aperture Delay (tA)
1.0
ns
Aperture Uncertainty Jitter (tJ)
0.5
0.3
ps rms
Wake-Up Time3
3.0
7.0
ms
OUT-OF-RANGE RECOVERY TIME
1
2
Cycles
1 For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40
models.
2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
tA
2.0ns MIN
tPD = 6.0ns MAX
03583-
002
N–9
N–8N–7N–6
N–5N–4
N–3N–2
N–1
N
ANALOG
INPUT
CLK
DATA
OUT
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram
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