參數(shù)資料
型號(hào)： AD9245BCPZRL7-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SGL 65MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 3
功率耗散（最大）： 300mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9245
Data Sheet
Rev. E | Page 22 of 32
03583-018
10
F
+
0.1
F
VREF
SENSE
R2
R1
0.5V
AD9245
VIN–
VIN+
REFT
0.1
F
0.1
F
10
F
0.1
F
REFB
SELECT
LOGIC
ADC
CORE
+
Figure 47. Programmable Reference Configuration
EXTERNAL REFERENCE OPERATION
The use of an external reference can be necessary to enhance
the gain accuracy of the ADC or improve thermal drift char-
acteristics. When multiple ADCs track one another, a single
reference (internal or external) can be necessary to reduce
gain matching errors to an acceptable level. Figure 48 shows
the typical drift characteristics of the internal reference in both
1.0 V and 0.5 V modes.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.0 V.
TEMPERATURE (°C)
VREF
ERROR
(%)
–40
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
80
70
60
50
40
30
20
10
0
–10
–20
–30
0358
3-
040
VREF = 0.5V
VREF = 1.0V
Figure 48. Typical VREF Drift
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9245 can output data in either
offset binary or twos complement format. There is also a
provision for enabling or disabling the clock DCS. The
MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined in Table 11.
Table 11. Mode Selection
MODE Voltage
Data Format
Duty Cycle Stabilizer
AVDD
Twos Complement
Disabled
2/3 AVDD
Twos Complement
Enabled
1/3 AVDD
Offset Binary
Enabled
AGND (Default)
Offset Binary
Disabled
EVALUATION BOARD
The AD9245 evaluation board provides the support circuitry
required to operate the ADC in its various modes and
configurations. Complete schematics and layout plots follow
and demonstrate the proper routing and grounding techniques
that should be applied at the system level.
It is critical that signal sources with very low phase noise
(<1 ps rms jitter) be used to realize the ultimate performance of
the converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
The AD9245 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input
configuration can be selected by proper connection of
various jumpers (refer to the schematics).
An alternative differential analog input path using an
AD8351 op amp is included in the layout but is not populated
in production. Designers interested in evaluating the op amp
with the ADC should remove C15, R12, and R3 and populate
the op amp circuit. The passive network between the AD8351
outputs and the AD9245 allows the user to optimize the
frequency response of the op amp for the application.
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