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參數(shù)資料
| 型號： | AD9244BSTZRL-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SGL 65MSPS 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 550mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9244
Rev. C | Page 18 of 36
A differential input structure allows the user to easily configure the
inputs for either single-ended or differential operation. The ADC’s
input structure allows the dc offset of the input signal to be varied
independent of the input span of the converter. Specifically, the
input to the ADC core can be defined as the difference of the
voltages applied at the VIN+ and VIN– input pins.
Therefore, the equation
VCORE = (VIN+) – (VIN)
(1)
defines the output of the differential input stage and provides
the input to the ADC core. The voltage, VCORE, must satisfy the
condition
VREF/2 < VCORE < VREF/2
(2)
where VREF is the voltage at the VREF pin.
In addition to the limitations placed on the input voltages VIN+
and VIN– by Equation 1 and Equation 2, boundaries on the
inputs also exist based on the power supply voltages according
to the conditions
AGND 0.3 V < VIN+ < AVDD + 0.3 V
(3)
AGND 0.3 V < VIN < AVDD + 0.3 V
(4)
where:
AGND is nominally 0 V.
AVDD is nominally 5 V.
The range of valid inputs for VIN+ and VIN is any combination
that satisfies Equation 2, Equation 3, and Equation 4.
For additional information showing the relationship between
VIN+, VIN–, VREF, and the analog input range of the AD9244,
ANALOG INPUT OPERATION
Figure 44 shows the equivalent analog input of the AD9244,
which consists of a 750 MHz differential SHA. The differential
input structure of the SHA is flexible, allowing the device to be
configured for either a differential or single-ended input. The
analog inputs VIN+ and VIN– are interchangeable, with the
exception that reversing the inputs to the VIN+ and VIN– pins
results in a data inversion (complementing the output word).
S
VIN+
VIN–
CPIN, PAR
S
H
CS
CH
CPIN, PAR
S
CH
02404-044
Figure 44. Analog Input of AD9244 SHA
Table 8. Analog Input Configuration Summary
Input
Input Range (V)
Input CM
Connection
Coupling
Span (V)
VIN+1
Voltage (V)
Comments
Single-Ended
DC or AC
1.0
0.5 to 1.5
1.0
Best for stepped input response applications.
2.0
1 to 3
2.0
Optimum noise performance for single-ended
mode often requires low distortion op amp
with VCC > 5 V due to its headroom issues.
Differential
DC or AC
1.0
2.25 to 2.75
2.75 to 2.25
2.5
Optimum full-scale THD and SFDR performance
well beyond the ADC’s Nyquist frequency.
2.0
2.0 to 3.0
3.0 to 2.0
2.5
Optimum noise performance for differential
mode. Preferred mode for applications.
1VIN+ and VIN can be interchanged if data inversion is required.
Table 9. Reference Configuration Summary
Reference Operating Mode
Connect
To
Resulting VREF (V)
Input Span (VIN+ VIN) (V p-p)
Internal
SENSE
VREF
1
Internal
SENSE
AGND
2
Internal
R1
VREF and SENSE
1 ≤ VREF ≤ 2.0
1 ≤ SPAN ≤ 2
R2
SENSE and REFGND
VREF = (1 + R1/R2)
(SPAN = VREF)
External
SENSE
AVDD
1 ≤ VREF ≤ 2.0
SPAN = EXTERNAL REF
VREF
EXTERNAL REF
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