- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10139 > AD9244BSTZRL-40 (Analog Devices Inc)IC ADC 14BIT SGL 40MSPS 48LQFP PDF資料下載
參數(shù)資料
| 型號： | AD9244BSTZRL-40 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SGL 40MSPS 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 300mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁
AD9244
Rev. C | Page 9 of 36
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input phase 180° and taking the peak measurement again. The
difference is then found between the two peak measurements.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Dual-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Effective Number of Bits (ENOB)
The ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD by
N = (SINAD 1.76)/6.02
Gain Error
The first code transition should occur at an analog value LSB
above negative full scale. The last code transition should occur
at an analog value 1 LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Common-Mode Rejection Ratio (CMRR)
Common-mode (CM) signals appearing on VIN+ and VIN–
are ideally rejected by the differential front end of the ADC.
With a full-scale CM signal driving both VIN+ and VIN–,
CMRR is the ratio of the amplitude of the full-scale input CM
signal to the amplitude of signal that is not rejected, expressed
in dBFS.1
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies are aliased
down into the first Nyquist zone (DC fCLOCK/2) on the output
of the ADC. Care must be taken that the bandwidth of the sam-
pled signal does not overlap Nyquist zones and alias onto itself.
Nyquist sampling performance is limited by the bandwidth of
the input SHA and clock jitter (noise caused by jitter increases
as the input frequency increases).
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs LSB before the first
code transition. Positive full scale is defined as a level 1 LSB
beyond the last code transition. The deviation is measured from
the middle of each particular code to the true straight line.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2).
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Power Supply Rejection Ratio (PSRR)
The change in full scale from the value with the supply at its
minimum limit to the value with the supply at its maximum limit.
Signal-to-Noise-and-Distortion (SINAD)1
T
he ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist
frequency, including harmonics, but excluding dc.
Signal-to-Noise Ratio (SNR)1
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7201LA12J | IC MEM FIFO 512X9 12NS 32-PLCC |
| MS3126E14-5P | CONN PLUG 5POS STRAIGHT W/PINS |
| AD7665ACPZRL | IC ADC 16BIT CMOS 5V 48LFCSP |
| LTC2858CMS-2#PBF | IC TXRX RS485/RS422 10-MSOP |
| VE-2T1-MY | CONVERTER MOD DC/DC 12V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9244BSTZRL-401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD9244BSTZRL-65 | 功能描述:IC ADC 14BIT SGL 65MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9244BSTZRL-651 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD9244-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40/65 MSPS Monolithic A/D Converter |
| AD9245 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 80 MSPS, 3 V A/D Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。