參數(shù)資料
型號(hào)： AD9238BCP-65EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/48頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL WITH AD9238BCP-65
設(shè)計(jì)資源： AD9238 Eval Brd Gerber File
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 640mW @ 65MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9238-65
已供物品： 板
相關(guān)產(chǎn)品： AD9238BCPZ-20-ND - IC ADC 12BIT DUAL 20MSPS 64LFCSP
AD9238BCPZ-40-ND - IC ADC 12BIT DUAL 40MSPS 64LFCSP
AD9238BCPZ-65-ND - IC ADC 12BIT DUAL 65MSPS 64LFCSP
AD9238BSTZRL-40-ND - IC ADC 12BIT DUAL 40MSPS 64LQFP
AD9238BCPZRL-65-ND - IC ADC 12BIT DUAL 65MSPS 64LFCSP
AD9238BCPZRL-20-ND - IC ADC 12BIT DUAL 20MSPS 64LFCSP
AD9238BCPZRL-40-ND - IC ADC 12BIT DUAL 40MSPS 64LFCSP
AD9238BSTZ-40-ND - IC ADC 12BIT DUAL 40MSPS 64-LQFP
AD9238BSTRL-40-ND - IC ADC 12BIT DUAL 40MSPS 64-LQFP
AD9238BST-40-ND - IC ADC 12BIT DUAL 40MSPS 64-LQFP
AD9238
Rev. C | Page 18 of 48
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9238 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
DIGITAL OUTPUTS
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
The AD9238 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
where N is the number of bits changing, and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9238 can be placed into standby mode
independently by asserting the PDWN_A or PDWN_B pins.
The data format can be selected for either offset binary or twos
complement. See the Data Format section for more information.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 1 mW for the ADC.
Note that if DCS is enabled, it is mandatory to disable the clock
of an independently powered-down channel. Otherwise,
significant distortion results on the active channel. If the clock
inputs remain active while in total standby mode, typical power
dissipation of 12 mW results.
TIMING
The AD9238 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propa-
gation delay (tPD) after the rising edge of the clock signal. Refer
to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the AD9238
using the DCS pin. This provides a stable 50% duty cycle to
internal circuits.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B =
HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled after a
power-down, the wake-up time is directly related to the recharging
of the REFT and REFB decoupling capacitors and to the duration
of the power-down. Typically, it takes approximately 5 ms to
restore full operation with fully discharged 0.1 μF and 10 μF
decoupling capacitors on REFT and REFB.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9238.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9238
is 1 MSPS. At clock rates below 1 MSPS, dynamic performance
may degrade.
B–8
A–7
B–7
A–6
B–6
A–5
B–5
A–4
B–4
A–3
B–3
A–2
B–2
A–1
B–1
A0
B0
A1
A–1
A0
A1
A2
A3
A4
A5
A6
A7
A8
B–1
B0
B1
B2
B3
B4
B5
B6
B7
B8
ANALOG INPUT
ADC A
ANALOG INPUT
ADC B
CLK_A = CLK_B =
MUX_SELECT
D0_A TO
D11_A
tPD
02640-066
Figure 34. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9238BCPZ-20 功能描述:IC ADC 12BIT DUAL 20MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD9238BCPZ-20EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter
AD9238BCPZ-250 制造商:Analog Devices 功能描述:12-BIT, 20 MSPS/40 MSPS/65 MSPSDUAL A/D CONVERTER - Trays
AD9238BCPZ-40 功能描述:IC ADC 12BIT DUAL 40MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD9238BCPZ-40EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter
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