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參數(shù)資料
| 型號(hào)： | AD9238 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| 中文描述： | 12位，20/40/65 MSPS雙通道的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | AD9238 |
AD9238
–3–
DC SPECIFICATIONS
Test
AD9238BST-20
Typ
AD9238BST-40
Min
Typ
AD9238BST-65
Min
Typ
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
*
DRVDD = 3.3 V
High Level Output Voltage
(IOH = 50 mA)
High Level Output Voltage
(IOH = 0.5 mA)
Low Level Output Voltage
(IOL = 50 mA)
Low Level Output Voltage
(IOL = 1.6 mA)
DRVDD = 2.5 V
High Level Output Voltage
(IOH = 50 mA)
High Level Output Voltage
(IOH = 0.5 mA)
Low Level Output Voltage
(IOL = 50 mA)
Low Level Output Voltage
(IOL = 1.6 mA)
Temp Level Min
Max
Max
Max
Unit
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
2.0
2.0
2.0
V
V
μA
μA
pF
0.8
+10
+10
0.8
+10
+10
0.8
+10
+10
–10
–10
–10
–10
–10
–10
2
2
2
Full
IV
3.29
3.29
3.29
V
Full
IV
3.25
3.25
3.25
V
Full
IV
0.05
0.05
0.05
V
Full
IV
0.2
0.2
0.2
V
Full
IV
2.49
2.49
2.49
V
Full
IV
2.45
2.45
2.45
V
Full
IV
0.05
0.05
0.05
V
Full
IV
0.2
0.2
0.2
V
*
Output Voltage Levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Test
AD9238BST-20
Typ
AD9238BST-40
Min
Typ
AD9238BST-65
Min
Typ
Parameter
SWITCHING PERFORMANCE
Max Conversion Rate
Min Conversion Rate
CLK Period
CLK Pulsewidth High
1
CLK Pulsewidth Low
1
DATA OUTPUT PARAMETERS
Output Delay
2
(t
PD
)
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty (t
J
)
Wake-Up Time
3
OUT-OF-RANGE RECOVERY TIME Full
Temp Level Min
Max
Max
Max
Unit
Full
Full
Full
Full
Full
VI
V
V
V
V
20
40
65
MSPS
MSPS
ns
ns
ns
1
1
1
50.0
15.0
15.0
25.0
8.8
8.8
15.4
6.2
6.2
Full
Full
Full
Full
Full
IV
V
V
V
V
V
2
3.5
7
1.0
0.5
2.5
1
6
2
3.5
7
1.0
0.5
2.5
1
6
2
3.5
7
1.0
0.5
2.5
2
6
ns
Cycles
ns
ps rms
ms
Cycles
NOTES
1
The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC 20).
2
Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.
3
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
Specifications subject to change without notice.
(continued)
REV. A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9238BST-20 | TV07RW21-35SD W/ PC CONT |
| AD9238BST-40 | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| AD9238BST-65 | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| AD9238BSTRL-20 | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| AD9238BSTRL-40 | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9238_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter |
| AD9238BCP-20EB | 制造商:Analog Devices 功能描述: |
| AD9238BCP-20EBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR AD9238 DUAL A/D CONVERTER ,12-BIT, 20 MSPS/40 MSPS/65 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9238 DUAL A/D CNVRTR ,12-BIT, 20 MSPS/40 MSPS/ - Bulk |
| AD9238BCP-40EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9238 DUAL A/D CNVRTR ,12-BIT, 20 MSPS/40 MSPS/ - Bulk |
| AD9238BCP-40EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9238 DUAL A/D CNVRTR ,12-BIT, 20 MSPS/40 MSPS/ - Bulk |
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