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參數資料
| 型號： | AD9235BCPZ-40 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 10/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SGL 40MSPS 32LFCSP |
| 標準包裝： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 40M |
| 數據接口： | 并聯 |
| 轉換器數目： | 3 |
| 功率耗散（最大）： | 165mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9235
Data Sheet
Rev. D | Page 18 of 40
Table 7. Reference Configuration Summary
Selected Mode
SENSE Voltage
Internal Switch Position
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
AVDD
N/A
2 × External Reference
Internal Fixed Reference
VREF
SENSE
0.5
1.0
Programmable Reference
0.2 V to VREF
SENSE
0.5 × (1 + R2/R1)
2 × VREF (See Figure 40)
Internal Fixed Reference
AGND to 0.2 V
Internal Divider
1.0
2.0
DIGITAL OUTPUTS
The AD9235 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
As detailed in Table 8, the data format can be selected for either
offset binary or twos complement.
Timing
The AD9235 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9235;
these transients can detract from the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9235 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9235. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9235, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).
Internal Reference Connection
A comparator within the AD9235 detects the potential at the
SENSE pin and configures the reference into one of four possi-
ble states, which are summarized in Table 7. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 39), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in Figure 40, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
VREF = 0.5 × (1 + R2/R1)
ADC
CORE
SELECT
LOGIC
AD9235
VIN–
VREF
SENSE
VIN+
REFB
REFT
10
F
0.1
F
0.1
F
10
F
0.1
F
0.1
F
0.5V
02461-039
+
Figure 39. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
02461-040
SENSE
ADC
CORE
SELECT
LOGIC
AD9235
VREF
VIN–
VIN+
REFB
REFT
10
F
0.1
F
0.1
F
10
F
0.1
F
0.1
F
0.5V
R2
R1
+
Figure 40. Programmable Reference Configuration
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