參數(shù)資料
型號： AD9230BCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 17/32頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 170MSPS 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 371mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，單極
AD9230
Rev. 0 | Page 24 of 32
600
–600
–400
–200
0
200
400
–3
–2
–1
0
1
2
3
EYE
D
IA
G
R
A
M
:
V
O
L
T
A
G
E
(
m
V
)
TIME (ns)
12
10
8
6
4
2
0
–100
0
100
T
IE
JI
T
E
R
HI
S
T
O
G
RAM
(H
it
s)
TIME (ps)
Figure 62. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9230-250
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 12.
If it is desired to change the output data format to twos comple-
An output clock signal is provided to assist in capturing data
from the AD9230. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data rate
mode (SDR), data is clocked out of the AD9230 and must be
captured on the rising edge of the DCO. In double data rate
mode (DDR), data is clocked out of the AD9230 and must be
captured on the rising and falling edges of the DCO See the
timing diagrams shown in Figure 2 and Figure 3 for more
information.
Output Data Rate and Pinout Configuration
The output data of the AD9230 can be configured to drive 12
pairs of LVDS outputs at the same rate as the input clock signal
(single data rate, or SDR, mode), or six pairs of LVDS outputs at
2× the rate of the input clock signal (double data rate, or DDR,
mode). SDR is the default mode; the device may be reconfigured
for DDR by setting Bit 3 in Register 14 (see Table 13).
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data. OR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range, as shown in
Figure 63. OR remains high until the analog input returns to
within the input range and another conversion is completed. By
logically AND-ing OR with the MSB and its complement, over-
range high or underrange low conditions can be detected.
1
0
1
OR DATA OUTPUTS
OR
+FS – 1 LSB
+FS – 1/2 LSB
+FS
–FS
–FS + 1/2 LSB
–FS – 1/2 LSB
1111
0000
1111
0000
1111
1110
0001
0000
06
00
2
-06
2
Figure 63. OR Relation to Input Voltage and Output Data
TIMING
The AD9230 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one
propagation delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9230.
These transients can degrade the converter’s dynamic performance.
The AD9230 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO.
The lowest typical conversion rate of the AD9230 is 40 MSPS.
At clock rates below 1 MSPS, the AD9230 assumes the standby
mode.
RBIAS
The AD9230 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resister should have a 1%
tolerance and is used to set the master current reference of the
ADC core.
AD9230 CONFIGURATION USING THE SPI
The AD9230 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
one-byte words. Each byte may be further divided down into
fields, which are documented in the Memory Map section.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK/DFS, SPI
SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used
to synchronize the read and write data presented the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB is an active low control that enables or
disables the read and write cycles (see Table 9).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9230BCPZ-210 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 12B 210Msps 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9230BCPZ-250 制造商:Analog Devices 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 56-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 250MSPS 12-BIT PARALLEL 56LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC ADC 12BIT 250MSPS LFCSP-56 制造商:Analog Devices Inc. 功能描述:Analog to Digital Converters - ADC 12-Bit 250 Msps ADC 制造商:Analog Devices 功能描述:IC, ADC, 12BIT, 250MSPS, LFCSP-56; Resolution (Bits):12bit; Sampling Rate:250MSPS; Supply Voltage Type:Single; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Supply Current:181mA; Digital IC Case Style:CSP; No. of Pins:56 ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:CONVERTER - ADC
AD9230BCPZRL7-170 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 12B 170Msps 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9230XCPZ-170 制造商:Analog Devices 功能描述:12-BIT, 170/210/250 MSPS 1.8 V A/D CONVERTER - Trays
AD9230XCPZ-210 制造商:Analog Devices 功能描述:12-BIT, 170/210/250 MSPS 1.8 V A/D CONVERTER - Trays
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