參數(shù)資料
型號(hào)： AD9229ABCPZRL7-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 65MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.47W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9229
Rev. B | Page 22 of 40
10
μF
0.1
μF
VREF
SENSE
0.5V
REFT
0.1
μF
0.1
μF
10
μF
0.1
μF
REFB
SELECT
LOGIC
ADC
CORE
+
04418-036
VIN–
VIN+
Figure 42. Internal Reference Configuration
10
μF
0.1
μF
VREF
0.5V
REFT
0.1
μF
0.1
μF
10
μF
0.1
μF
REFB
SELECT
LOGIC
ADC
CORE
+
04418-037
VIN–
VIN+
SENSE
R2
R1
Figure 43. Programmable Reference Configuration
If the internal reference of the AD9229 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 44
depicts how the internal reference voltage is affected by loading.
ILOAD (mA)
VREF
ERRO
R
(%)
0.05
–0.20
–0.15
–0.30
–0.35
–0.25
–0.05
0
–0.10
0
1.8
2.0
1.6
1.2
1.4
1.0
0.8
0.6
0.4
0.2
04418-
058
VREF = 0.5V
VREF = 1.0V
Figure 44. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 45 shows the typical drift characteristics of the
internal reference.
TEMPERATURE (
°C)
VR
EF
ER
R
OR
(
%
)
0.10
0
–0.04
–0.02
–0.08
–0.10
–0.06
0.08
0.04
0.06
0.02
–40
65
80
50
35
20
5
–10
–25
04418-057
VREF = 0.5V
VREF = 1.0V
Figure 45. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. The external
reference is loaded with an equivalent 7 kΩ load. An internal
reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
external reference must be limited to a maximum of 1 V.
Power and Ground Recommendations
When connecting power to the AD9229, it is recommended
that two separate 3.0 V supplies be used: one for analog
(AVDD) and one for digital (DRVDD). If only one supply is
available, it should be routed to the AVDD first and tapped off
and isolated with a ferrite bead or filter choke with decoupling
capacitors proceeding. The user can employ several different
decoupling capacitors to cover both high and low frequencies.
These should be located close to the point of entry at the PC
board level and close to the parts with minimal trace length.
A single PC board ground plane should be sufficient when
using the AD9229. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance is easily achieved.
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