參數(shù)資料
型號(hào)： AD9228ABCPZ-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/56頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SPI/SRL 65M 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 510mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
Data Sheet
AD9228
Rev. E | Page 3 of 56
REVISION HISTORY
12/11—Rev. D to Rev. E
Changes to Output Signals Section and Figure 71......................37
Change to Default Operation and Jumper Selection Settings
Section ..............................................................................................38
Change to Figure 74 ........................................................................41
Added Endnote 3 in Ordering Guide ...........................................53
4/10—Rev. C to Rev. D
Changes to Table 16 ........................................................................35
Updated Outline Dimensions........................................................53
Changes to Ordering Guide...........................................................53
12/09—Rev. B to Rev. C
Updated Outline Dimensions........................................................53
Changes to Ordering Guide...........................................................54
7/07—Rev. A to Rev. B
Changes to Figure 3...........................................................................7
Change to Table 7 ............................................................................10
5/07—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Change to Effective Number of Bits (ENOB)................................4
Changes to Logic Output (SDIO/ODM) Section..........................5
Added Endnote 3 to Table 3.............................................................5
Changes to Pipeline Latency............................................................6
Added Endnote 2 to Table 4.............................................................6
Changes to Figure 2 to Figure 4.......................................................7
Changes to Figure 10 ......................................................................12
Changes to Figure 15, Figure 17 to Figure 19, Figure 37, and
Figure 39 ......................................................................................14
Changes to Figure 23 to Figure 26 Captions ...............................15
Change to Figure 35 Caption.........................................................17
Added Figure 46 and Figure 47 .....................................................20
Changes to Figure 51 ......................................................................21
Changes to Clock Duty Cycle Considerations Section ..............22
Changes to Power Dissipation and Power-Down Mode Section ...23
Changes to Figure 61 to Figure 63 Captions ...............................25
Changes to Table 9 Endnote ..........................................................26
Changes to Digital Outputs and Timing Section........................27
Added Table 10 ................................................................................27
Changes to RBIAS Pin Section......................................................28
Deleted Figure 62 and Figure 63 ...................................................27
Changes to Figure 67 ......................................................................29
Changes to Hardware Interface Section.......................................30
Added Figure 68 ..............................................................................31
Changes to Table 15 ........................................................................31
Changes to Reading the Memory Map Table Section ................32
Change to Input Signals Section ...................................................36
Changes to Output Signals Section...............................................36
Changes to Figure 71 ......................................................................36
Changes to Default Operation and
Jumper Selection Settings Section ...........................................37
Changes to Alternative Analog Input
Drive Configuration Section ....................................................38
Changes to Figure 74 ......................................................................40
Changes to Table 17 ........................................................................48
Changes to Ordering Guide...........................................................52
4/06—Revision 0: Initial Version
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AD9228ABCPZRL7-40 功能描述:IC ADC 12BIT SPI/SRL 40M 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD9228ABCPZRL7-65 功能描述:IC ADC 12BIT SPI/SRL 65M 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD9228BCPZ-40 制造商:Analog Devices 功能描述:ADC Quad Pipelined 40Msps 12-bit Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC SM 12-BIT ADC QUAD WAFFLE125 制造商:Analog Devices 功能描述:IC 12BIT ADC QUAD 40MSPS LFCSP48 制造商:Analog Devices 功能描述:IC, 12BIT ADC, QUAD 40MSPS, LFCSP48
AD9228BCPZ-65 制造商:Analog Devices 功能描述:ADC Quad Pipelined 65Msps 12-bit Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC 12BIT ADC QUAD 65MSPS LFCSP48
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