參數(shù)資料
型號(hào)： AD9228-65EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9228
設(shè)計(jì)資源： AD9219/28/59/87 Gerber Files
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 4
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 119mW @ 65MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9228
已供物品： 板，電源
Data Sheet
AD9228
Rev. E | Page 31 of 56
SERIAL PORT INTERFACE (SPI)
The AD9228 serial port interface allows the user to configure the
converter for specific functions or operations through a structured
register space provided in the ADC. This may provide the user
with additional flexibility and customization, depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, as documented
in the Memory Map section. Detailed operational information
can be found in the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
There are three pins that define the SPI: SCLK, SDIO, and CSB
(see Table 14). The SCLK pin is used to synchronize the read
and write data presented to the ADC. The SDIO pin is a dual-
purpose pin that allows data to be sent to and read from the
internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 14. Serial Port Pins
Pin
Function
SCLK
Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO
Serial Data Input/Output. A dual-purpose pin. The typical
role for this pin is as an input or output, depending on
the instruction sent and the relative position in the
timing frame.
CSB
Chip Select Bar (Active Low). This control gates the read
and write cycles.
The falling edge of the CSB in conjunction with the rising edge of
the SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted followed by
one or more data bytes, which is determined by Bit Field W0 and
Bit Field W1. An example of the serial timing and its definitions
can be found in Figure 69 and Table 15. During normal operation,
CSB is used to signal to the device that SPI commands are to be
received and processed. When CSB is brought low, the device
processes SCLK and SDIO to obtain instructions. Normally,
CSB remains low until the communication cycle is complete.
However, if connected to a slow device, CSB can be brought
high between bytes, allowing older microcontrollers enough
time to transfer data into shift registers. CSB can be stalled
when transferring one, two, or three bytes of data. When W0
and W1 are set to 11, the device enters streaming mode and
continues to process data, either reading or writing, until
CSB is taken high to end the communication cycle. This allows
complete memory transfers without requiring additional instruc-
tions. Regardless of the mode, if CSB is taken high in the middle
of a byte transfer, the SPI state machine is reset and the device
waits for a new instruction.
In addition to the operation modes, the SPI port configuration
influences how the AD9228 operates. For applications that do
not require a control port, the CSB line can be tied and held high.
This places the remainder of the SPI pins into their secondary
modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin
sections. CSB can also be tied low to enable 2-wire mode. When
CSB is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, the user should ensure that the serial port remains
synchronized with the CSB line when using this mode. When
operating in 2-wire mode, it is recommended to use a 1-, 2-,
or 3-byte transfer exclusively. Without an active CSB line,
streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the SDIO pin to change from an
input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 14 compose the physical interface
between the user’s programming device and the serial port of
the AD9228. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
If multiple SDIO pins share a common connection, care should
be taken to ensure that proper VOH levels are met. Assuming the
same load for each AD9228, Figure 68 shows the number of
SDIO pins that can be connected together and the resulting VOH
level. This interface is flexible enough to be controlled by either
serial PROMS or PIC mi
crocontrollers, providing the user with
an alternative method, other than a full SPI controller, to
program the ADC (see the AN-812 Application Note).
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