- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10128 > AD9226ASTZRL (Analog Devices Inc)IC ADC 12BIT 65MSPS 48LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9226ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 22/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 65MSPS 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 475mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
REV. B
–3–
AD9226
DIGITAL SPECIFICATIONS
Parameters
Temp
Test Level
Min
Typ
Max
Unit
LOGIC INPUTS (Clock, DFS
1, Duty Cycle1, and
Output Enable
1)
High-Level Input Voltage
Full
IV
2.4
V
Low-Level Input Voltage
Full
IV
0.8
V
High-Level Input Current (VIN = AVDD)
Full
IV
–10
+10
A
Low-Level Input Current (VIN = 0 V)
Full
IV
–10
+10
A
Input Capacitance
Full
V
5
pF
Output Enable
1
Full
IV
V
LOGIC OUTPUTS (With DRVDD = 5 V)
High-Level Output Voltage (IOH = 50
A)
Full
IV
4.5
V
High-Level Output Voltage (IOH = 0.5 mA)
Full
IV
2.4
V
Low-Level Output Voltage (IOL = 1.6 mA)
Full
IV
0.4
V
Low-Level Output Voltage (IOL = 50
A)
Full
IV
0.1
V
Output Capacitance
5pF
LOGIC OUTPUTS (With DRVDD = 3 V)
High-Level Output Voltage (IOH = 50
A)
Full
IV
2.95
V
High-Level Output Voltage (IOH = 0.5 mA)
Full
IV
2.80
V
Low-Level Output Voltage (IOL = 1.6 mA)
Full
IV
0.4
V
Low-Level Output Voltage (IOL = 50
A)
Full
IV
0.05
V
NOTES
1LQFP package.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameters
Temp
Test Level
Min
Typ
Max
Unit
Max Conversion Rate
Full
VI
65
MHz
Clock Period
1
Full
V
15.38
ns
CLOCK Pulsewidth High
2
Full
V
3
ns
CLOCK Pulsewidth Low
2
Full
V
3
ns
Output Delay
Full
V
3.5
7
ns
Pipeline Delay (Latency)
Full
V
7
Clock Cycles
Output Enable Delay
3
Full
V
15
ns
NOTES
1The clock period may be extended to 10
s without degradation in specified performance @ 25°C.
2When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.
3LQFP package.
Specifications subject to change without notice.
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)
(TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n
ANALOG
INPUT
CLOCK
DATA
OUT
n–8
n–7
n–6
n–5
n–4
n–3
n–2
n+1
n
n–1
TOD = 7.0 MAX
3.5 MIN
Figure 1. Timing Diagram
DRVDD
2
05
– .
DRVDD
2
05
+ .
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS3126F12-8SY | CONN PLUG 8POS STRAIGHT W/SCKT |
| IDT7204L50P | IC FIFO ASYNCH 4KX9 50NS 28DIP |
| IDT7202LA15P | IC FIFO ASYNCH 1KX9 15NS 28DIP |
| MS3126F12-8SX | CONN PLUG 8POS STRAIGHT W/SCKT |
| LT1328CS8#TR | IC RECEIVER IR 4MBPS IRDA 8SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9226-EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9226 ADC CNVRTR - Bulk |
| AD9226-LQFP-EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit, 65 MSPS ADC Converter |
| AD9226QFP-EB | 制造商:Analog Devices 功能描述:12-BIT 50 MSPS ADC 制造商:Analog Devices 功能描述:EVAL BD FOR AD9226 ADC CNVRTR - Bulk |
| AD9228 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9228_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。