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參數(shù)資料
| 型號： | AD9225ARZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/25頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 25MSPS 28SOIC |
| 標準包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 7 |
| 功率耗散（最大）： | 373mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，單極 |
–20–
AD9225
AIN (dBFS)
90
95
–15
0
SNR/SFDR
(dBFS)
–10
–5
85
70
55
50
100
80
75
65
60
SFDR
DUAL-TONE
(dBFS)
SNR
SINGLE-TONE
(dBc)
SFDR
SINGLE-TONE
(dBFS)
Figure 29. IF Undersampling at 70 MHz (F1 = 69.50 MHz,
F2 = 70.11 MHz, CLOCK = 25 MHz)
AIN (dBFS)
90
95
–15
0
SNR/SFDR
(dBFS)
–10
–5
85
70
55
50
100
80
75
65
60
SFDR
DUAL-TONE
(dBFS)
SNR
SINGLE-TONE
(dBc)
SFDR
SINGLE-TONE
(dBFS)
Figure 30. IF Undersampling at 85 MHz (F1 = 84.81 MHz,
F2 = 85.23 MHz, CLOCK = 20 MHz)
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
The minimization of the loop area encompassed by a signal
and its return path.
The minimization of the impedance associated with ground
and power paths.
The inherent distributed capacitor formed by the power
plane, PCB insulation and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement
in performance.
It is important to design a layout that prevents noise from cou-
pling onto the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. While the AD9225 features separate analog
and driver ground pins, it should be treated as an analog com-
ponent. The AVSS and DRVSS pins must be joined together
directly under the AD9225. A solid ground plane under the
ADC is acceptable if the power and ground return currents are
carefully managed. Alternatively, the ground plane under the
ADC may contain serrations to steer currents in predictable
directions where cross coupling between analog and digital
would otherwise be unavoidable. The AD9225/AD9225EB
ground layout, shown in Figure 38, depicts the serrated type
of arrangement.
The board is built primarily over a common ground plane. It
has a slit to route currents near the clock driver. Figure 31 illus-
trates a general scheme of ground and power implementation, in
and around the AD9225.
ANALOG
CIRCUITS
DIGITAL
LOGIC
ICs
V
A
D
DVSS
AVSS
A
B
IA
ID
AVDD
DVDD
LOGIC
SUPPLY
D
A
VIN
CSTRAY
GND
A
= ANALOG
D
= DIGITAL
ADC
IC
DIGITAL
CIRCUITS
A
Figure 31. Ground and Power Consideration
Analog and Digital Driver Supply Decoupling
The AD9225 features separate analog and driver supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals. In general, AVDD, the analog supply, should
be decoupled to AVSS, the analog common, as close to the
chip as physically possible. Figure 32 shows the recommended
decoupling for the analog supplies; 0.1
mF ceramic chip and
10
mF tantalum capacitors should provide adequately low imped-
ance over a wide frequency range. Note that the AVDD and
AVSS pins are co-located on the AD9225 to simplify the layout
of the decoupling capacitors and provide the shortest possible
PCB trace lengths. The AD9225/AD9225EB power plane layout,
shown in Figure 39 depicts a typical arrangement using a multi-
layer PCB.
0.1 F
AVDD
AVSS
AD9225
10 F
Figure 32. Analog Supply Decoupling
The CML is an internal analog bias point used internally by
the AD9225. This pin must be decoupled with at least a 0.1
mF
capacitor as shown in Figure 33. The dc level of CML is
approximately AVDD/2. This voltage should be buffered if it is
to be used for any external biasing.
0.1 F
CML
AD9225
Figure 33. CML Decoupling
Rev. C
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| AD9226ARS | 功能描述:IC ADC 12BIT 65MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD9226ARSRL | 功能描述:IC ADC 12BIT 65MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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