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參數(shù)資料
| 型號(hào)： | AD9222BCPZ-50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 8-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 5/56頁 |
| 文件大小： | 2026K |
| 代理商： | AD9222BCPZ-50 |
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AD9222
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Rev. 0 | Page 5 of 56
Table 3.
Parameter
1
CLOCK INPUTS (CLK+, CLK)
Logic Compliance
Differential Input Voltage
2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)
3
Logic 1 Voltage (I
OH
= 800 μA)
Logic 0 Voltage (I
OL
= 50 μA)
DIGITAL OUTPUTS (D+, D), (ANSI-644)
1
Logic Compliance
Differential Output Voltage (V
OD
)
Output Offset Voltage (V
OS
)
Output Coding (Default)
DIGITAL OUTPUTS (D+, D),
(Low Power, Reduced Signal Option)
1
Logic Compliance
Differential Output Voltage (V
OD
)
Output Offset Voltage (V
OS
)
Output Coding (Default)
1
See the AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation
, for a complete set of definitions and how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.
AD9222-40
Typ
CMOS/LVDS/LVPECL
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
1.125
Offset binary
AD9222-50
Typ
CMOS/LVDS/LVPECL
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
1.125
Offset binary
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min
Max
Min
Max
250
1.2
0
1.2
0
1.2
0
247
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.2
1.2
1.2
0
247
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
Full
Full
150
1.10
LVDS
Offset binary
250
1.30
150
1.10
LVDS
Offset binary
250
1.30
mV
V
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