參數(shù)資料
型號: AD9222ABCPZRL7-65
廠商: Analog Devices Inc
文件頁數(shù): 45/60頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SRL 65MSPS 64LFCSP
標準包裝: 750
位數(shù): 12
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 950.5mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 16 個單端,單極;8 個差分,單極
Data Sheet
AD9222
Rev. F | Page 5 of 60
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Table 3.
AD9222-40
AD9222-50
AD9222-65
Parameter1
Temp
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
250
mV p-p
Input Common-Mode Voltage
Full
1.2
V
Input Resistance (Differential)
25°C
20
k
Input Capacitance
25°C
1.5
pF
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Full
1.2
3.6
1.2
3.6
1.2
3.6
V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
3.6
1.2
3.6
1.2
3.6
V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance
25°C
70
k
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Full
1.2
DRVDD+ 0.3
1.2
DRVDD+ 0.3
1.2
DRVDD+0.3
V
Logic 0 Voltage
Full
0
0.3
0
0.3
0
0.3
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
2
pF
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (D + x, D x),
(ANSI-644)1
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
454
247
454
247
454
mV
Output Offset Voltage (VOS)
Full
1.125
1.375
1.125
1.375
1.125
1.375
V
Output Coding (Default)
Offset binary
DIGITAL OUTPUTS (D + x, D x),
(Low Power, Reduced Signal
Option)1
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
250
150
250
150
250
mV
Output Offset Voltage (VOS)
Full
1.10
1.30
1.10
1.30
1.10
1.30
V
Output Coding (Default)
Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.
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