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| 型號： | AD9219BCPZ-65 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 4-CH 10-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC48 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 1571K |
| 代理商： | AD9219BCPZ-65 |
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AD9219
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
A
) due only to aperture jitter (t
J
) can be calculated by
SNR degradation
= 20 × log 10 [1/2 × π ×
f
A
×
t
J
]
Rev. 0 | Page 22 of 52
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 55).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9219.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the
AN-501 Application Note
and the
AN-756
Application Note
for more in-depth information about jitter
performance as it relates to ADCs (visit
www.analog.com
).
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
0
RMS CLOCK JITTER REQUIREMENT
S
Figure 55. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 56 and Figure 57, the power dissipated by
the AD9219 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined primarily
by the DRVDD supply and bias current of the LVDS output drivers.
0
C
P
ENCODE (MSPS)
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
180
200
220
240
260
280
300
320
340
360
0
20
40
60
80
100
120
140
15
20
25
30
35
40
10
Figure 56. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz, f
SAMPLE
= 40 MSPS
0
0
C
P
ENCODE (MSPS)
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
20
40
60
80
100
120
140
160
180
200
10
20
30
40
50
60
250
270
290
310
330
350
370
390
Figure 57. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz, f
SAMPLE
= 65 MSPS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9219 | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9219-65EB | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9219BCPZRL-65 | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9219BCPZRL-40 | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9219BCPZ-40 | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9219BCPZRL-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9219BCPZRL-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9220 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters |
| AD9220AR | 功能描述:IC ADC 12BIT 10MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD9220AR-REEL | 功能描述:IC ADC 12BIT 10MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
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