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參數(shù)資料
| 型號： | AD9219BCPZ-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 4-CH 10-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC48 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 1571K |
| 代理商： | AD9219BCPZ-40 |
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AD9219
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02), device
index and transfer register map (Address 0x05 and Address 0xFF),
and program register map (Address 0x08 to Address 0x25).
Rev. 0 | Page 31 of 52
The left-hand column of the memory map indicates the register
address number in hexadecimal. The default value of this address is
shown in hexadecimal in the right-hand column. The Bit 7 (MSB)
column is the start of the default hexadecimal value given. For
example, Hexadecimal Address 0x09, Clock, has a hexadecimal
default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0,
Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001
in binary. This setting is the default for the duty cycle stabilizer in
the on condition. By writing a 0 to Bit 6 at this address the duty
cycle stabilizer turns off. For more information on this and other
functions, consult the user manual
Interfacing to High Speed
ADCs via SPI
.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 15, where an X refers
to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9219BCPZ-65 | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 65Msps 10-bit Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC 10BIT ADC QUAD 65MSPS LFCSP48 |
| AD9219BCPZRL-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9219BCPZRL-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
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| AD9220AR | 功能描述:IC ADC 12BIT 10MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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