參數(shù)資料
型號(hào)： AD9219-65EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/56頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD9219
設(shè)計(jì)資源： AD9219/28/59/87 Gerber Files
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 4
位數(shù)： 10
采樣率（每秒）： 40M
數(shù)據(jù)接口： 串行
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 378mW @ 1.8V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9219
已供物品： 板
Data Sheet
AD9219
Rev. E | Page 29 of 56
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test
pattern if it and the CSB pin are held high during device power-
up. When SCLK/DTP is tied to AVDD, the ADC channel
outputs shift out the following pattern: 1000 0000 0000. The
FCO and DCO function normally while all channels shift out the
repeatable test pattern. This pattern allows the user to perform
timing alignment adjustments among the FCO, DCO, and output
data. For normal operation, this pin should be tied to AGND
through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant.
Table 12. Digital Test Pattern Pin Settings
Selected DTP
DTP Voltage
Resulting
D + x and D x
Resulting
FCO and DCO
Normal
Operation
10 kΩ to AGND
Normal
operation
Normal operation
DTP
AVDD
1000 0000 0000
Normal operation
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored. This pin is both 1.8 V and
3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The
resistor current is derived on-chip and sets the AVDD current
of the ADC to a nominal 232 mA at 65 MSPS. Therefore, it is
imperative that at least a 1% tolerance on this resistor be used to
achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the
AD9219. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2 V p-p. The VREF is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
improve accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9219. The recommended capacitor values and
configurations for the AD9219 reference pin are shown in
Table 13. Reference Settings
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting
Differential
Span (V p-p)
External
Reference
AVDD
N/A
2 × external
reference
Internal,
2 V p-p FSR
AGND to 0.2 V
1.0
2.0
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