參數(shù)資料
型號(hào)： AD9215BCP-80EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/36頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9215BCP-80
設(shè)計(jì)資源： Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Interfacing the High Frequency AD8331 to AD9215 (CN0096)
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： 1 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 104mW @ 80MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9215-80
已供物品： 板
相關(guān)產(chǎn)品： AD9215BRUZ-80-ND - IC ADC 10BIT 80MSPS 3V 28TSSOP
AD9215BRUZ-65-ND - IC ADC 10BIT 65MSPS 3V 28TSSOP
AD9215BRUZRL7-105-ND - IC ADC 10BIT 105MSPS 3V 28TSSOP
AD9215BRUZRL7-65-ND - IC ADC 10BIT 65MSPS 3V 28TSSOP
AD9215BRUZRL7-80-ND - IC ADC 10BIT 80MSPS 3V 28TSSOP
AD9215BRUZ-105-ND - IC ADC 10BIT 105MSPS 3V 28-TSSOP
AD9215BCPZ-105-ND - IC ADC 10BIT 105MSPS 3V 32-LFCSP
AD9215BRU-105-ND - IC ADC 10BIT 105MSPS 3V 28-TSSOP
AD9215BCPZ-80-ND - IC ADC 10BIT 80MSPS 32LFCSP
AD9215BCPZ-65-ND - IC ADC 10BIT 65MSPS 32-LFCSP
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AD9215
Data Sheet
Rev. B | Page 16 of 36
Table 7. Reference Configuration Summary
Selected Mode
External SENSE
Connection
Internal Op Amp
Configuration
Resulting VREF
(V)
Resulting Differential Span
(V p-p)
Externally Supplied Reference
AVDD
N/A
2 × External Reference
Internal 0.5 V Reference
VREF
Voltage Follower (G = 1)
0.5
1.0
Programmed Variable
Reference
External Divider
Noninverting (1 < G < 2)
0.5 × (1 + R2/R1)
2 × VREF
Internally Programmed 1 V
Reference
AGND to 0.2 V
Internal Divider
1.0
2.0
Table 8. Digital Output Coding
Code
VIN+ VIN Input Span =
2 V p-p (V)
VIN+ VIN Input Span =
1 V p-p (V)
Digital Output Offset Binary
(D9D0)
Digital Output Twos
Complement (D9D0)
1023
1.000
0.500
11 1111 1111
01 1111 1111
512
0
10 0000 0000
00 0000 0000
511
0.00195
0.000978
01 1111 1111
11 1111 1111
0
1.00
0.5000
00 0000 0000
10 0000 0000
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tA) can be
calculated with the following equation
SNR Degradation = 20 × log10 [2 × π × fINPUT × tA]
In the equation, the rms aperture jitter, tA, represents the root-
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9215. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last
step.
Power Dissipation and Standby Mode
As shown in Figure 35, the power dissipated by the AD9215 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
where N is the number of output bits, 10 in the case of the
AD9215. This maximum current is for the condition of every
output bit switching on every clock cycle, which can only occur
for a full-scale square wave at the Nyquist frequency, fCLOCK/2. In
practice, the DRVDD current is established by the average
number of output bits switching, which are determined by the
encode rate and the characteristics of the analog input signal.
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in Fig-
ure 35 was taken with a 5 pF load on each output driver.
02874-A-075
15
35
30
25
20
40
105
5
15
25
35
45
55
65
75
85
95
I AVDD
(mA)
I DRVDD
–1
1
3
5
7
9
11
13
15
fSAMPLE (MSPS)
AD9215-105 IAVDD
AD9215-65/80 IAVDD
IDRVDD
Figure 35. Supply Current vs. fSAMPLE for fIN = 10.3 MHz
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
By asserting the PDWN pin high, the AD9215 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9215 into its normal opera-
tional mode.
In standby mode, low power dissipation is achieved by shutting
down the reference, reference buffer, and biasing networks. The
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