- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1985 > AD9212ABCPZ-65 (Analog Devices Inc)IC ADC 10BIT SRL 65MSPS 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9212ABCPZ-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/56頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT SRL 65MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 833mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 16 個單端，單極；8 個差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
AD9212
Data Sheet
Rev. E | Page 20 of 56
THEORY OF OPERATION
The AD9212 architecture consists of a pipelined ADC divided
into three sections: a 4-bit first stage followed by eight 1.5-bit
stages and a 3-bit flash. Each stage provides sufficient overlap
to correct for flash errors in the preceding stage. The quantized
outputs from each stage are combined into a final 10-bit result
in the digital correction logic. The pipelined architecture permits
the first stage to operate with a new input sample while the
remaining stages operate with preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9212 is a differential switched-
capacitor circuit designed for processing differential input signals.
This circuit can support a wide common-mode range while
maintaining excellent performance. An input common-mode
voltage of midsupply minimizes signal-dependent errors and
provides optimum performance.
SS
H
CPAR
CSAMPLE
CPAR
VIN – x
H
SS
H
VIN + x
H
0
59
68
-0
17
Figure 42. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 42). When the input
circuit is switched into sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low-Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of low-
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a shunt capacitor or two
single-ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs; and the Analog Dialogue article “Transformer-Coupled
Front-End for Wideband A/D Converters” (Volume 39, April 2005)
for more information. In general, the precise values depend on
the application.
The analog inputs of the AD9212 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 45 and Figure 46.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9214BRS-RL65 | IC ADC 10BIT 65MSPS 28-SSOP |
| AD9215BRU-105 | IC ADC 10BIT 105MSPS 3V 28-TSSOP |
| AD9216BCPZ-105 | IC ADC 10BIT DL 105MSPS 64LFCSP |
| AD9218BST-105 | IC ADC 10BIT DUAL 105MSPS 48LQFP |
| AD9219ABCPZRL7-65 | IC ADC 10BIT SRL 65MSPS 64LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9212ABCPZRL7-40 | 功能描述:IC ADC 10BIT SRL 40MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9212ABCPZRL7-65 | 功能描述:IC ADC 10BIT SRL 65MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9212BCPZ-40 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 40Msps 10-bit Serial 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10BIT ADC 40/65MSPS 1.8V SMD 制造商:Analog Devices 功能描述:IC, 10BIT ADC, 40/65MSPS, 1.8V, SMD |
| AD9212BCPZ-65 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 65Msps 10-bit Serial 64-Pin LFCSP EP |
| AD9212BCPZRL7-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。