參數(shù)資料
型號： AD9211_07
廠商： Analog Devices, Inc.
英文描述： 10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter
中文描述： 10位，200 MSPS/250 MSPS/300 MSPS的，1.8 V模擬到數(shù)字轉換器
文件頁數(shù)： 9/28頁
文件大小： 1180K
代理商： AD9211_07
AD9211
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 9 of 28
DNC = DO NOT CONNECT
Figure 4. AD9211 Single Data Rate Mode Pin Configuration
PIN 1
1
2
3
4
5
6
7
8
9
D1–
D1+
D2–
D2+
D3–
D3+
DRVDD
DRGND
D4–
D4+
D5–
D5+
D6–
D6+
10
11
12
13
14
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
36 VIN–
37 AVDD
38 AVDD
39 AVDD
40 CML
41 AVDD
42 AVDD
1
D
1
D
1
D
1
2
O
2
(
2
O
2
D
2
D
2
S
2
S
2
C
2
R
1
D
4
4
4
4
4
5
5
5
5
5
4
4
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
AD9211
5
5
0
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No.
Mnemonic
30, 32 to 34, 37 to 39,
41 to 43, 46
7, 24, 47
DRVDD
0
AGND
1
8, 23, 48
DRGND
1
35
VIN+
36
VIN
40
CML
Description
1.8 V Analog Supply.
AVDD
1.8 V Digital Output Supply.
Analog Ground.
Digital Output Ground.
Analog Input—True.
Analog Input—Complement.
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN.
Clock Input—True.
Clock Input—Complement.
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V.
CMOS-Compatible Chip Reset (Active Low).
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode).
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
Do Not Connect.
D0 Complement Output Bit (LSB).
D0 True Output Bit (LSB).
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
44
45
31
28
25
CLK+
CLK
RBIAS
RESET
SDIO/DCS
26
27
29
49
50
51 to 54
55
56
1
2
3
4
5
6
9
10
SCLK/DFS
CSB
PWDN
DCO
DCO+
DNC
D0
D0+
D1
D1+
D2
D2+
D3
D3+
D4
D4+
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