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| 型號(hào)： | AD9204BCPZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 80MSPS DL 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；2 個(gè)差分，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
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AD9204
Rev. 0 | Page 25 of 36
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
]
)
10
/
(
LF
SNR
In the previous equation, the rms aperture jitter represents
the clock input jitter specification. Input frequency (IF)
undersampling applications are particularly sensitive to jitter,
as illustrated in Figure 56.
80
75
70
65
60
55
50
45
1
10
100
1k
FREQUENCY (MHz)
S
NR
(
d
BF
S
)
0.5ps
0.2ps
0.05ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
0
812
2-
0
22
Figure 56. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9204.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
See the AN-501 Application Note and the AN-756 Application
Note available on www.analog.com for more information.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the analog core power dissipated by
the AD9204 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs is determined primarily
by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (30, in the case of the
AD9204).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 57 was
taken using the same operating conditions as those used in the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
140
120
100
80
60
50
0
10
20
30
40
50
60
70
80
CLOCK RATE (MSPS)
ANAL
O
G
CO
R
E
P
O
W
E
R
(
m
W
)
08
12
2-
05
1
130
110
90
70
AD9204-80
AD9204-65
AD9204-40
AD9204-20
Figure 57. AD9204 Analog Core Power vs. Clock Rate
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