參數(shù)資料
型號(hào)： AD9203ARUZRL7
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 5/28頁(yè)
文件大小： 0K
描述： IC ADC 10BIT 40MSPS 3V 28-TSSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 10
采樣率（每秒）： 40M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 5
功率耗散（最大）： 108mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；1 個(gè)差分，單極
其它名稱(chēng)： AD9203ARUZRL7-ND
AD9203ARUZRL7TR
AD9203
00573-
021
0.1
F
10
F
Rev. B | Page 13 of 28
ADC
CORE
+
–
LOGIC
AINP
AINN
VREF
0.5V
REFTF
REFBF
REFSENSE
1.5V
0V
1.875V
1.125V
AD9203
0.1
F
0.1
F
0.1
F
10
F
RB
RA
Figure 21. Programmable Reference Configuration
EXTERNAL REFERENCE OPERATION
Figure 22 illustrates the use of an external reference. An
external reference may be necessary for several reasons. Tighter
reference tolerance will enhance the accuracy of the ADC and
will allow lower temperature drift performance. When several
ADCs track one another, a single reference (internal or
external) will be necessary. The AD9203 will draw less power
when an external reference is used.
When the REFSENSE pin is tied to AVDD, the internal
reference will be disabled, allowing the use of an external
reference.
The AD9203 contains an internal reference buffer. It will load
the external reference with an equivalent 10 k load. The
internal buffer will generate positive and negative full-scale
references for the ADC core.
In Figure 22, an external reference is used to set the midscale set
point for single-ended use. At the same time, it sets the input
voltage span through a resistor divider. If the ADC is being
driven differentially through a transformer, the external
reference can set the center tap (common-mode voltage).
00573-022
10
F
0.1
F
0.1
F
0.1
F
1.0V
2.0V
VREF
AD9203
5V
1.5k
3.0V
REFSENSE
A3
AVDD
AINP
AINN
EXTERNAL
REF (2V)
1V
1.5k
Figure 22. External Reference Configuration
CLAMP OPERATION
The AD9203 contains an internal clamp. It may be used when
operating the input in a single-ended mode. This clamp is very
useful for clamping NTSC and PAL video signals to ground.
The clamp cannot be used in the differential input mode.
00573-023
1V p-p
0V DC
REFSENSE
VREF
AINN
CIN
CLAMPIN
CLAMP
AD9203
AINP
SW1
50
TYP
ADC
CORE
Figure 23. Clamp Configuration (VREF = 0.5 V)
Figure 23 shows the internal clamp circuitry and the external
control signals needed for clamp operation. To enable the
clamp, apply a logic high 1 to the CLAMP pin. This will close
SW1, the internal switch. SW1 is opened by asserting the
CLAMP pin low 0. The capacitor holds the voltage across CIN
constant until the next interval. The charge on the capacitor will
leak off as a function of input bias current (see Figure 24).
–50
250
200
150
100
50
0
0.5
1.0
1.5
2.0
2.5
3.0
00573-024
INPUT VOLTAGE (V)
IN
P
U
T
BI
AS
(
A)
Figure 24. Input Bias Current vs. Input Voltage (FS = 40 MSPS)
DRIVING THE ANALOG INPUT
Figure 25 illustrates the equivalent analog input of the AD9203,
(a switched capacitor input). Bringing CLK to a logic high,
opens S3 and closes S1 and S2. The input source connected to
AIN and must charge Capacitor CH during this time. Bringing
CLK to a logic low opens S2, and then S1 opens followed by
closing S3. This puts the input in the hold mode.
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