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參數(shù)資料
| 型號： | AD9148BBPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/72頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SPI/SRL 196BGA |
| 標準包裝： | 1 |
| 系列： | TxDAC+® |
| 設(shè)置時間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.67W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 196-BGA |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 1G |
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AD9148
Data Sheet
Rev. B | Page 28 of 72
Register Name
Addr
(Hex)
Bit
Name
Function
Default
Event Flag 0 (All bits
are high when interrupt
is active. Clear interrupt
by writing respective
bit high.)
06
7
PLL lock lost
1 = indicates that the PLL that was previously locked has
unlocked from the reference signal.
0
6
PLL lock
1 = indicates that the PLL has locked to the reference clock
input.
0
5
Sync lock lost
1 = indicates that the sync logic that was previously locked
has lost alignment.
0
4
Sync lock
1 = indicates that the sync logic achieved sync alignment. This
is indicated when no phase changes are requested for at least
a few full averaging cycles.
0
2
FIFO SPI aligned
1 = indicates that a FIFO reset originating from a serial port-
based request has successfully completed.
0
1
FIFO Warning 1
1 = indicates that the difference between the FIFO read and
write pointers is 1.
0
FIFO Warning 2
1 = indicates that the difference between the FIFO read and
write pointers is 2.
0
Event Flag 1(All bits are
high when interrupt is
active. Clear interrupt
by writing respective
bit high).
07
4
AED compare pass
1 = indicates that the SED logic detected a valid input data
pattern comparison against the preprogrammed expected
values.
0
3
AED compare fail
1 = indicates that the SED logic detected an invalid input data
pattern comparison against the preprogrammed expected
values. This automatically clears when eight valid I/Q data
pairs are received.
0
2
SED compare fail
1 = indicates that the SED logic detected an invalid input data
pattern comparison against the preprogrammed expected
values.
0
Clock Receiver Control
08
7
CLK duty
correction
Enables duty-cycle correction on CLK input.
0
6
REFCLK duty
correction
Enables duty-cycle correction on REFCLK input.
0
5
CLK cross
correction
Enables differential crossing correction on CLK input.
1
4
REFCLK cross
correction
Enables differential crossing correction on REFCLK input.
1
3:0
0111
Always set these bits to 0111
0111
PLL Control 0
0A
7
PLL enable
Enables PLL clock multiplier.
0
6
PLL manual
enable
Enables PLL band selection mode (0 = auto, and 1 = manual). 1
5:0
Manual VCO band
VCO band used in manual mode.
0
PLL Control 1
0C
7:5
PLL loop bandwidth Selects PLL loop filter bandwidth.
110
000 = narrowest bandwidth.
…
111 = widest bandwidth.
4:0
01001
Set these bits to 01001 for optimal PLL operation.
10001
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| AD9148BBPZRL | 功能描述:IC DAC 16BIT SPI/SRL 196BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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| AD9148-M5372-EBZ | 功能描述:BOARD EVAL FOR AD9149, ADL5372 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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