參數(shù)資料
型號(hào)： AD9117BCPZRL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/52頁(yè)
文件大?。?/td> 0K
描述： IC DAC DUAL 14BIT LO PWR 40LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： High CMRR Circuit for Converting Wideband Complementary DAC Outputs to Single-Ended Without Precision Resistors (CN0142)
標(biāo)準(zhǔn)包裝： 750
系列： TxDAC®
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 232mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 4 電流，單極
采樣率（每秒）： 125M
Data Sheet
AD9114/AD9115/AD9116/AD9117
Rev. C | Page 39 of 52
Register
Address
Bit
Name
Description
Memory R/W
0x12
7
CALRSTQ
0 (default): no action.
1: clears CALSTATQ.
6
CALRSTI
0 (default): no action.
1: clears CALSTATI.
4
CALEN
0 (default): no action.
1: initiates device self-calibration.
3
SMEMWR
0 (default): no action.
1: writes to static memory (calibration coefficients).
2
SMEMRD
0 (default): no action.
1: reads from static memory (calibration coefficients).
1
UNCALQ
0 (default): no action.
1: resets Q DAC calibration coefficients to default (uncalibrated).
0
UNCALI
0 (default): no action.
1: resets I DAC calibration coefficients to default (uncalibrated).
CLKMODE
0x14
7:6
CLKMODEQ[1:0]
Depending on CLKMODEN bit setting, these two bits reflect the phase relationship
between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retime.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
4
Searching
Datapath retimer status bit.
0 (default): clock relationship established.
1: indicates that the internal datapath retimer is searching for clock relationship
(device output is not usable while this bit is high).
3
Reacquire
Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
2
CLKMODEN
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read
back in CLKMODEI[1:0] and CLKMODEQ[1:0].
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers.
1:0
CLKMODEI[1:0]
Depending on CLKMODEN bit setting, these two bits reflect the phase relationship
between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Version
0x1F
7:0
Version[7:0]
Hardware version of the device. This register is set to 0x0A for the latest version of
the device.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9117-DPG2-EBZ 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
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