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參數(shù)資料
| 型號： | AD9054ABSTZ-200 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 200MSPS 44-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 781mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 6 個(gè)單端，雙極；1 個(gè)差分，雙極 |
AD9054A
–5–
REV. D
AIN
D7–D0
ENCODE
SAMPLE N–1
SAMPLE N
SAMPLE N+3
SAMPLE N+4
SAMPLE N+2
SAMPLE N+1
tA
tEH
tEL
1/fS
tPD
tV
DATA N
DATA N–1
DATA N–2
DATA N–3
DATA N–4
DATA N–5
Figure 1. Timing—Single Channel Mode
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Function
1
ENCODE
Encode Clock for ADC (ADC
Samples on Rising Edge
of ENCODE)
2
ENCODE
Encode Clock Complement
(ADC Samples on Falling Edge
of
ENCODE)
3, 5, 15, 18, 28,
VDD
Power Supply (5 V)
30, 31, 36, 41
4, 6, 16, 17, 27,
GND
Ground
29, 32, 35, 37, 40
14–7
DA0–DA7
Digital Outputs of ADC Channel
A. DA7 is the MSB, DA0 the LSB
19–26
DB0–DB7
Digital Outputs of ADC Channel
B. DB7 is the MSB, DB0 the LSB
33
VREF OUT
Internal Reference Output
(2.5 V typical); Bypass with
0.1
F to Ground
34
VREF IN
Reference Input for ADC (2.5 V
typical,
±4%)
38
AIN
Analog Input—Complement.
Connect to input signal midscale
reference.
39
AIN
Analog Input—True
42
DEMUX
Format Select. LOW = Dual.
Channel Mode, HIGH = Single.
Channel Mode (Channel A Only)
43
DS
Data Sync Complement
44
DS
Data Sync—Aligns Output Chan-
nels in Dual-Channel Mode
PIN CONFIGURATION
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
DB1
DB2
DB3
GND
DA2
DA1
DA0 (LSB)
VDD
GND
VDD
DB0 (LSB)
VREF
OUT
GND
VDD
GND
VDD
GND
ENCODE
VDD
GND
VDD
GND
DA
7
(MSB)
DA
6
DA
5
DA
4
DA
3
DB
7
(MSB)
DB
6
DB
5
DB
4
DS
DEMUX
VDD
GND
AIN
GND
VDD
GND
VREF IN
AD9054A
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| AD9054APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit, 200 MSPS A/D Converter |
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