參數(shù)資料
型號(hào): AD9054ABSTZ-135
廠商: Analog Devices Inc
文件頁數(shù): 4/20頁
文件大?。?/td> 0K
描述: IC ADC 8BIT 135MSPS 44-LQFP
產(chǎn)品培訓(xùn)模塊: ADC Applications
ADC Architectures
ADC DC/AC Performance
標(biāo)準(zhǔn)包裝: 1
位數(shù): 8
采樣率(每秒): 135M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 700mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-LQFP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 5 個(gè)單端,雙極;1 個(gè)差分,雙極
產(chǎn)品目錄頁面: 780 (CN2011-ZH PDF)
AD9054A
–12–
REV. D
APPLICATION NOTES
THEORY OF OPERATION
The AD9054A combines Analog Devices’ patented MagAmp
bit-per-stage architecture with flash converter technology to
create a high performance, low power ADC. For ease of use the
part includes an on-board reference and input logic that accepts
TTL, CMOS or PECL levels.
The analog input signal is buffered by a high-speed differential
amplifier and applied to a track-and-hold (T/H) circuit. This T/H
captures the value of the input at the sampling instant and
maintains it for the duration of the conversion. The sampling
and conversion process is initiated by a rising edge on the
ENCODE input. Once the signal is captured by the T/H, the
four Most Significant Bits (MSBs) are sequentially encoded by
the MagAmp string. The residue signal is then encoded by a
flash comparator string to generate the four Least Significant
Bits (LSBs). The comparator outputs are decoded and com-
bined into the 8-bit result.
If the user has selected Single Channel Mode (
DEMUX =
HIGH), the 8-bit data word is directed to the Channel A out-
put bank. Data are strobed to the output on the rising edge of
the ENCODE input with four pipeline delays. If the user has
selected Dual Channel Mode (
DEMUX = LOW) the data are
alternately directed between the A and B output banks and have
five pipeline delays. At power-up, the N sample data can appear
at either the A or B port. To align the data in a known state the
user must strobe DATA SYNC (DS,
DS) per the conditions
described in the Timing section.
Graphics Applications
The high bandwidth and low power of the AD9054A make it very
attractive for applications that require the digitization of presampled
waveforms, wherein the input signal rapidly slews from one
level to another and is relatively stable for a period of time.
Examples of these include digitizing the output of computer
graphic display systems and very high speed solid state imagers.
These applications require the converter to process inputs with
frequency components well in excess of the sampling rate (often
with subnanosecond rise times), after which the A/D must settle
and sample the input in well under one pixel time. The architec-
ture of the AD9054A is vastly superior to older flash architectures,
that not only exhibit excessive input capacitance (which is very
hard to drive), but can make major errors when fed a very rap-
idly slewing signal. The AD9054A’s extremely wide bandwidth
Track/Hold circuit processes these signals without difficulty.
Using the AD9054A
Good high speed design practices must be followed when using
the AD9054A. To obtain maximum benefit, decoupling capaci-
tors should be physically as close to the chip as possible. We
recommend placing a 0.1
F capacitor at each power-ground
pin pair (9 total) for high frequency decoupling, and including
one 10
F capacitor for local low frequency decoupling. The
VREF IN pin should also be decoupled by a 0.1
F capacitor.
The part should be located on a solid ground plane and output
trace lengths should be short (<1 inch) to minimize transmis-
sion line effects. This avoids the need for termination resistors
on the output bus and reduces the load capacitance that needs
to be driven, which in turn minimizes on-chip noise due to
heavy current flow in the outputs. We have obtained optimum
performance on our evaluation board by tying all VDD pins to a
quiet analog power supply system, and tying all GND pins to a
quiet analog system ground.
Minimum Encode Rate
The minimum sampling rate for the AD9054A is 25 MHz.
To achieve very high sampling rates, the track/hold circuit
employs a very small hold capacitor. When operated below the
minimum guaranteed sampling rate, the T/H droop becomes
excessive. This is first observed as an increase in offset voltage,
followed by degraded linearity at even lower frequencies.
Lower effective sampling rates may be easily supported by oper-
ating the converter in dual port output mode and using only
one output channel. A majority of the power dissipated by the
AD9054A is static (not related to conversion rate) so the penalty
for clocking at twice the desired rate is not high.
Reference
The AD9054A internal reference, VREF, provides a simple, cost
effective reference for many applications. It exhibits reasonable
accuracy and excellent stability over power supply and tempera-
ture variations. The VREF OUT pin can simply be strapped to
the VREF IN pin. The internal reference can be used to drive
additional loads (up to several mA), including multiple A/D con-
verters as might be required in a triple video converter application.
When an external reference is desired for accuracy or other
requirements, the AD9054A should be driven directly by the
external reference source connected to pin VREF IN (VREF
OUT can be left floating). The external reference can be set to
2.5 V
± 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the
analog full-scale range will increase by 10% to 1.024
× 1.1 =
1.1264 V. The new input range will then be
AIN
±0.5632 V.
TAMB – C
VREF
OUT
Volts
2.502
2.501
2.498
–40
100
–20
0
20
40
60
80
2.500
2.499
TPC 25. Reference Voltage vs. Temperature
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