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參數(shù)資料
| 型號： | AD9054A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit, 200 MSPS A/D Converter |
| 中文描述： | 8位，200 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 332K |
| 代理商： | AD9054A |
AD9054A
–15–
REV. B
EVALUATION BOARD
The AD9054A evaluation board offers an easy way to test the
AD9054A. It provides dc biasing for the analog input, generates
the latch clocks for both full speed and demuxed modes, and in-
cludes a reconstruction DAC. The board has several different
modes of operation, and is shipped in the following configuration:
DC-Coupled Analog Input
Demuxed Outputs
Differential Clocks
Internal Voltage Reference.
VREF OUT
VREF IN
AIN
AIN
DEMUX
AD9054A
DS
DS
ENC
ENC
B PORT
'574
A PORT
'574
DAC
CLK A
CLK B
CLOCKING
ENC
ENC
S102
VREF EXT
S103
DC BIAS
50
AIN
5V
D FF
D
C
RESET
BUTTON
CLK A
CLK B
S104
S105
ENC
50
ENC
50
Figure 37. PCB Block Diagram
Analog Input
The evaluation board accepts a 1 V input signal centered at
ground. The board’s input circuitry then biases this signal to
+2.5 V in one of two ways:
1. DC-coupled through an AD9631 op amp; this is the mode in
which it is shipped. Potentiometer R7 provides adjustment
of the bias voltage.
2. AC-coupled through C1.
These two modes are selected by jumpers S101 and S103. For
dc coupling, the S101 jumper is connected between the two left
pins and the S103 jumper is connected between the two lower
pins. For ac coupling, the S101 jumper is connected between
the two right pins and the S103 jumper is connected between
the two upper pins.
ENCODE
The AD9054A ENCODE input can be driven two ways:
1. Differential TTL, CMOS, or PECL; it is shipped in this
mode.
2. Single-ended TTL or CMOS. To use in this mode, remove
R11, the 50
chip resistor located next to the
ENCODE
input, and insert a 0.1
μ
F ceramic capacitor into the C5 slot.
C5 is located between the ENC connector and the ENCODE
input to the DUT and is marked on the back side of the
board. In this mode,
ENCODE
is biased with internal resis-
tors to 1.5 V, but it can be externally driven to any dc voltage.
Voltage Reference
The AD9054A has an internal 2.5 V voltage reference. An
external reference may be employed instead. The evaluation
board is configured for the internal reference. To use an exter-
nal reference, connect it to the (VREF) pin on the power con-
nector and move jumper S102.
Single Port Mode
Single Port Mode sets the AD9054A to produce data on every
clock cycle on output port A only. To test in this mode, jumper
S104 should be set to single channel and S106 and S107 must
be set to F (for Full). The maximum speed in single port mode
is 100 MSPS.
Dual Port Mode
Dual Port or half speed output mode sets the ADC to produce
data alternately on Port A and Port B. In this mode, the reset
function should be implemented. To test in this mode, set
jumper S104 to Dual Channel, and set S106 and S107 to D (for
Dual Port). The maximum speed in this mode is 200 MSPS.
RESET
RESET drives the AD9054A’s Data Sync (DS) pins. When
operating in Single Port Mode, RESET is not used. In Dual-
Channel Mode it is needed for two reasons: to synchronize the
timing of Port A data and Port B data with a known clock edge,
as described in the data sheet, and to synchronize the evaluation
board’s latch clocks with the data coming out of the AD9054A.
Reset can be driven in two ways: by pushing the reset button on
the board, or externally, with a TTL pulse through connector J5
or J6.
DAC Out
The DAC output is a representation of the data on output Port
A only. Output Port B is not reconstructed.
Troubleshooting
If the board does not seem to be working correctly, try the fol-
lowing:
Check that all jumpers are in the correct position for the
desired mode of operation.
Push the reset button. This will align the AD9054A’s data
output with the half speed latch clocks.
Switch the jumper S105 from A-R to R-B or vice-versa, then
push the reset button. In demuxed mode, this will have the
effect of inverting the half speed latch clocks.
At high encode rates, the evaluation board’s clock generation
circuitry is sensitive to the +5 V digital power supply. At
high encode rates, the +5 V digital power should be kept
below +5.2 V. This is an evaluation board sensitivity and
not an AD9054A sensitivity.
The AD9054A Evaluation Board is provided as a design ex-
ample for customers of Analog Devices, Inc. ADI makes no
warranties, express, statutory, or implied, regarding merchant-
ability or fitness for a particular purpose.
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| AD9054ABSTZ-135 | 功能描述:IC ADC 8BIT 135MSPS 44-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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