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參數(shù)資料
| 型號： | AD8804AR |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT 12CH W/SD 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 系列： | TrimDAC® |
| 設(shè)置時(shí)間： | 600ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 12 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 60µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 12 電壓，單極 |
| 采樣率（每秒）： | 1.7M |
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
STATIC ACCURACY
Specifications apply to all DACs
Resolution
N
8
Bits
Differential Nonlinearity Error
DNL
Guaranteed Monotonic
–1
±1/4
+1
LSB
Integral Nonlinearity Error
INL
–1.5
±1/2
+1.5
LSB
Full-Scale Error
GFSE
–1
1/2
+1
LSB
Zero Code Error
VZSE
–1
1/4
+1
LSB
DAC Output Resistance
ROUT
35
8
k
Output Resistance Match
R/R
O
1.5
%
REFERENCE INPUT
Voltage Range
2
VREFH
0VDD
V
VREFL
Pin Available on AD8804 Only
0
VDD
V
REFH Input Resistance
RREFH
Digital Inputs = 55H, VREFH = VDD
1.2
k
REFL Input Resistance
3
RREFL
Digital Inputs = 55H, VREFL = VDD
1.2
k
Reference Input Capacitance
3
CREF0
Digital Inputs all Zeros
32
pF
CREF1
Digital Inputs all Ones
32
pF
DIGITAL INPUTS
Logic High
VIH
VDD = +5 V
2.4
V
Logic Low
VIL
VDD = +5 V
0.8
V
Logic High
VIH
VDD = +3 V
2.1
V
Logic Low
VIL
VDD = +3 V
0.6
V
Input Current
IIL
VIN = 0 V or + 5 V
±1
A
Input Capacitance
3
CIL
5pF
POWER SUPPLIES
4
Power Supply Range
VDD Range
2.7
5.5
V
Supply Current (CMOS)
IDD
VIH = VDD or VIL = 0 V
0.01
10
A
Supply Current (TTL)
IDD
VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V
1
4
mA
Shutdown Current
IREFH
SHDN
= 0
0.2
10
A
Power Dissipation
PDISS
VIH = VDD or VIL = 0 V, VDD = +5.5 V
55
W
Power Supply Sensitivity
PSRR
VDD = +5 V ± 10%
0.001
0.002
%/%
DYNAMIC PERFORMANCE
3
VOUT Settling Time
tS
±1/2 LSB Error Band
0.6
s
Crosstalk
CT
Between Adjacent Outputs
5
50
dB
SWITCHING CHARACTERISTICS
3, 6
Input Clock Pulse Width
tCH, tCL
Clock Level High or Low
15
ns
Data Setup Time
tDS
5ns
Data Hold Time
tDH
5ns
CS
Setup Time
tCSS
10
ns
CS
High Pulse Width
tCSW
10
ns
Reset Pulse Width
tRS
90
ns
CLK Rise to CS Rise Hold Time
tCSH
20
ns
CS
Rise to Clock Rise Setup
tCS1
10
ns
NOTES
1Typicals represent average readings at +25
°C.
2V
REFH can be any value between GND and V DD, for the AD8804 VREFL can be any value between GND and VDD.
3Guaranteed by design and not subject to production test.
4Digital Input voltages V
IN = 0 V or VDD for CMOS condition. DAC outputs unloaded. P DISS is calculated from (IDD × VDD).
5Measured at a V
OUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz).
6See timing diagram for location of measured values. All input control voltages are specified with t
R = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
AD8802/AD8804–SPECIFICATIONS
REV. 0
–2–
(VDD = +3 V
10% or +5 V
10%, VREFH = +VDD, VREFL = 0 V, –40 C
≤T
A
≤ +85 C unless otherwise noted)
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