參數(shù)資料
型號: AD8804AN
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 12 Channel, 8-Bit TrimDACs with Power Shutdown
中文描述: 12, SERIAL INPUT LOADING, 0.6 us SETTLING TIME, 8-BIT DAC, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 11/16頁
文件大?。?/td> 432K
代理商: AD8804AN
AD8802/AD8804
REV. 0
–11–
; This 8051
μ
C subroutine loads an AD8802 or AD8804 DAC with an 8-bit value,
; using the 8051’s parallel port #1.
; The DAC value is stored at location DAC_VALUE
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
PORT1
DATA
DAC_VALUE
DATA
DAC_ADDR
DATA
LOOPCOUNT
DATA
;
ORG
LD_8804:
ORL
CLR
MOV
MOV
RR
RR
RR
RR
ACALL
MOV
MOV
ACALL
SETB
RET
90H
40H
41H
43H
;SFR register for port 1
;DAC Value
;DAC Address (0 through 7)
;COUNT LOOPS
100H
PORT1,#11110000B
PORT1.5
LOOPCOUNT,#4
A,DAC_ADDR
A
A
A
A
SEND_SERIAL
LOOPCOUNT,#8
A,DAC_VALUE
SEND_SERIAL
PORT1.5
;arbitrary start
;set CLK, /CS and /SHDN high
;Set Chip Select low
;Address is 4 bits
;Get DAC address
;Rotate the DAC
;address to the Most
;Significant Bits (MSBs)
;
;Send the address
;Do 8 bits of data
;Send the data
;Set /CS high
;DONE
SEND_SERIAL:
RLC
MOV
CLR
SETB
DJNZ
RET;
END
A
PORT1.7,C
PORT1.6
PORT1.6
LOOPCOUNT,SEND_SERIAL
;Move next bit to carry
;Move data to SDI
;Pulse the
;CLK input
;Loop if not done
Listing 2. Software for the 8051 to AD8802/AD8804 Parallel Port Interface
An MC68HC11-to-AD8802/AD8804 Interface
Like the 8051
μ
C, the MC68HC11 includes a dedicated serial
data port (labeled SPI). The SPI port provides an easy interface
to the AD8802/AD8804 (Figure 27). The interface uses three
lines of Port D for the serial data, and one or two lines from
Port C to control the
SHDN
and
RS
(AD8802 only) inputs.
SDI
CLK
CS
SHDN
RS (
AD8802 ONLY)
AD8802/
AD8804*
MC68HC11*
MOSI
SCK
SS
PC0
PC1
(PD3)
(PD4)
(PD5)
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. An AD8802/AD8804-to-MC68HC11 Interface
A software routine for loading the AD8802/AD8804 from a
68HC11 evaluation board is shown in Listing 3. First, the
MC68HC11 is configured for SPI operation. Bits CPHA and
CPOL define the SPI mode wherein the serial clock (SCK) is
high at the beginning and end of transmission, and data is valid
on the rising edge of SCK. This mode matches the requirements
of the AD8802/AD8804. After the registers are saved on the
stack, the DAC value and address are transferred to RAM and
the AD8802/AD8804’s
CS
is driven low. Next, the DAC’s ad-
dress byte is transferred to the SPDR register, which automati-
cally initiates the SPI data transfer. The program tests the SPIF
bit and loops until the data transfer is complete. Then the DAC
value is sent to the SPI. When transmission of the second byte is
complete,
CS
is driven high to load the new data and address
into the AD8802/AD8804.
相關(guān)PDF資料
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