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參數(shù)資料
| 型號： | AD8803AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Octal 8-Bit TrimDAC with Power Shutdown |
| 中文描述： | OCTAL, SERIAL INPUT LOADING, 0.6 us SETTLING TIME, 8-BIT DAC, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 213K |
| 代理商： | AD8803AN |
REV. A
–4–
AD8801/AD8803
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DAC REGISTER LOAD
1
0
1
0
1
0
+5V
0V
SDI
CLK
CS
V
OUT
OCTAL 8-BIT TRIMDAC,
WITH SHUTDOWN
Figure 2a. Timing Diagram
A
X
OR D
X
A
X
OR D
X
1
0
1
0
1
0
+5V
0V
SDI
(DATA
IN)
CLK
CS
V
OUT
±
1 LSB
±
1 LSB ERROR BAND
t
S
t
CSW
t
CSH
t
CL
t
CSS
t
CH
t
DS
t
DH
t
CS1
DETAIL SERIAL DATA INPUT TIMING (
RS
= "1")
Figure 2b. Detail Timing Diagram
t
S
t
RS
±
1 LSB
±
1 LSB ERROR BAND
1
0
+5V
2.5V
RS
V
OUT
RESET TIMING
Figure 2c. Reset Timing Diagram
T able I. Serial-Data Word Format
ADDR
B10 B9
DAT A
B7
B8
B6
B5
B4
B3
B2
B1
B0
A2
MSB
2
10
A1
A0
LSB MSB
2
8
D7
D6
D5
D4
D3
D2
D1
L SB
2
1
D0
2
9
2
7
2
6
2
5
2
4
2
3
2
2
2
0
OPE RAT ION
T he AD8801/AD8803 provides eight channels of programmable
voltage output adjustment capability. Changing the programmed
output voltage of each T rimDAC is accomplished by clocking in
an 11-bit serial data word into the SDI (Serial Data Input) pin.
T he format of this data word is three address bits, MSB first,
followed by eight data bits, MSB first. T able I provides the se-
rial register data word format. T he AD8801/AD8803 has the
following address assignments for the ADDR decode which de-
termines the location of DAC register receiving the serial regis-
ter data in bits B7 through B0:
DAC
# =
A
2
×
4 +
A
1
×
2 +
A
0 + 1
DAC outputs can be changed one at a time in random se-
quence. T he fast serial-data loading of 33 MHz makes it possible
to load all eight DACs in as little time as 3
μ
s (12
×
8
×
30 ns).
T he exact timing requirements are shown in Figure 2.
T he AD8801 offers a midscale preset activated by the
RS
pin
simplifying initial setting conditions at first power up. T he
AD8803 has both a V
REFH
and a V
REFL
pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown
SHDN
that places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply,
V
REF
inputs, and all 8 outputs. In shutdown mode the DACx
latch settings are maintained. When returning to operational
mode from power shutdown the DAC outputs return to their
previous voltage settings.
MSB
O
X
2R
R
P CH
N CH
TO OTHER DACS
R
2R
2R
2R
.
.
.
GND
V
REFL
LSB
DAC
REGISTER
D6
D0
D7
V
REFH
Figure 3. AD8801/AD8803 Equivalent TrimDAC Circuit
PROGRAMMING T HE OUT PUT VOLT AGE
T he output voltage range is determined by the external refer-
ence connected to V
REFH
and V
REFL
pins. See Figure 3 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8801, its V
REFL
is internally connected to GND and
therefore cannot be offset. V
REFH
can be tied to V
DD
and V
REFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. T he general
transfer equation that determines the programmed output
voltage is:
V
O
(
Dx
) = (
Dx
)/256
×
(
V
REFH
–
V
REFL
) +
V
REFL
(1)
where
Dx
is the data contained in the 8-bit DACx latch.
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