VDD
參數(shù)資料
型號(hào)： AD8802ARZ-REEL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 13/16頁(yè)
文件大?。?/td> 0K
描述： IC DAC 8BIT 12CH W/SD 20SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
系列： TrimDAC®
設(shè)置時(shí)間： 600ns
位數(shù)： 8
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 12
電壓電源： 單電源
功率耗散（最大）： 60µW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 12 電壓，單極
采樣率（每秒）： 1.7M
AD8802/AD8804
REV. 0
–6–
HOURS OF OPERATION AT 150
°C
0.04
–0.04
0
–0.02
0.02
0
600
200
300
500
VDD = +4.5V
VREF = +4.5V
SS = 176 PCS
x + 2
σ
CHANGE
IN
FULL-SCALE
ERROR
–
LSB
x
x – 2
σ
100
400
Figure 13. Full-Scale Error Accelerated by Burn-In
HOURS OF OPERATION AT 150
°C
1.0
–1.0
0
–0.5
0.5
INPUT
RESISTANCE
DRIFT
–
k
0
600
200
300
400
VDD = +4.5V
VREF = +4.5V
CODE = 55H
SS = 176 PCS
x + 2
σ
x
x – 2
σ
100
500
Figure 14. REF Input Resistance Accelerated by Burn-In
OPERATION
The AD8802/AD8804 provides twelve channels of program-
mable voltage output adjustment capability. Changing the pro-
grammed output voltage of each DAC is accomplished by
clocking in a 12-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is four address bits,
MSB first, followed by 8 data bits, MSB first. Table I provides
the serial register data word format. The AD8802/AD8804 has
the following address assignments for the ADDR decode which
determines the location of the DAC register receiving the serial
register data in Bits B7 through B0:
DAC# = A3
× 8 + A2 × 4 + A1 × 2 + A0 + 1
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it pos-
sible to load all 12 DACs in as little time as 4.6
s (13
× 12 ×
30 ns). The exact timing requirements are shown in Figure 15.
Table I. Serial-Data Word Format
ADDR
DATA
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1 D0
MSB
LSB MSB
LSB
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
The AD8802 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power-up. The
AD8804 has both a VREFH and a VREFL pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN which places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply
and VREF inputs. In shutdown mode the DACX register settings
are maintained. When returning to operational mode from
power shutdown the DAC outputs return to their previous volt-
age settings.
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DAC REGISTER LOAD
1
0
1
0
1
0
+5V
0V
SDI
CLK
CS
VOUT
Figure 15a. Timing Diagram
AX OR DX
1
0
1
0
1
0
+5V
0V
SDI
(DATA IN)
CLK
CS
VOUT
±1/2 LSB
±1/2 LSB ERROR BAND
tCSH
tCL
tCSS
tDS
tDH
tCS1
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
tCSW
tCH
tS
Figure 15b. Detail Timing Diagram
tS
tRS
±1 LSB
±1 LSB ERROR BAND
1
0
+5V
2.5V
RS
VOUT
RESET TIMING
Figure 15c. Reset Timing Diagram
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