參數(shù)資料
型號: AD8625ARZ
廠商: Analog Devices Inc
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC OPAMP JFET 5MHZ QUAD 14SOIC
標準包裝: 56
放大器類型: J-FET
電路數(shù): 4
輸出類型: 滿擺幅
轉換速率: 5 V/µs
增益帶寬積: 5MHz
電流 - 輸入偏壓: 0.25pA
電壓 - 輸入偏移: 350µV
電流 - 電源: 710µA
電流 - 輸出 / 通道: 15mA
電壓 - 電源,單路/雙路(±): 5 V ~ 26 V,±2.5 V ~ 13 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 14-SOIC
包裝: 管件
產品目錄頁面: 773 (CN2011-ZH PDF)
Data Sheet
AD8625/AD8626/AD8627
Rev. F | Page 13 of 20
APPLICATIONS INFORMATION
The AD862x is one of the smallest and most economical
JFETs offered. It has true single-supply capability and has
an input voltage range that extends below the negative rail,
allowing the part to accommodate input signals below ground.
The rail-to-rail output of the AD862x provides the maximum
dynamic range in many applications. To provide a low offset,
low noise, high impedance input stage, the AD862x uses
n-channel JFETs. The input common-mode voltage extends
from 0.2 V below –VS to 2 V below +VS. Driving the input of
the amplifier, configured in the unity gain buffer, closer than
2 V to the positive rail causes an increase in common-mode
voltage error, as illustrated in Figure 15, and a loss of amplifier
bandwidth. This loss of bandwidth causes the rounding of the
output waveforms shown in Figure 39 and Figure 40, which
have inputs that are 1 V and 0 V from +VS, respectively.
The AD862x does not experience phase reversal with input
signals close to the positive rail, as shown in Figure 29. For
input voltages greater than +VSY, a resistor in series with the
AD862x’s noninverting input prevents phase reversal at the
expense of greater input voltage noise. This current-limiting
resistor should also be used if there is a possibility of the input
voltage exceeding the positive supply by more than 300 mV, or
if an input voltage is applied to the AD862x when ±VSY = 0.
Either of these conditions damages the amplifier if the
condition exists for more than 10 seconds. A 10 k resistor
allows the amplifier to withstand up to 10 V of continuous
overvoltage, while increasing the input voltage noise by a
negligible amount.
TIME (2
s/DIV)
03023-038
VOLTAGE
(2V/DIV)
INPUT
OUTPUT
VSY = 5V
4V
0V
Figure 39. Unity Gain Follower Response to 0 V to 4 V Step
TIME (2
s/DIV)
03023-039
VOLTAGE
(2V/DIV)
INPUT
OUTPUT
VSY = 5V
4V
0V
5V
0V
Figure 40. Unity Gain Follower Response to 0 V to 5 V Step
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