參數(shù)資料
型號: AD8610ARZ
廠商: Analog Devices Inc
文件頁數(shù): 7/24頁
文件大?。?/td> 0K
描述: IC OPAMP JFET 25MHZ PREC 8SOIC
產(chǎn)品培訓(xùn)模塊: Power Line Monitoring
Top Five Problems in Photodiode Opamp Circuits
設(shè)計資源: Precision, AC Reference Signal Attenuator Using AD5546/56 Multiplying DAC (CN0025)
標(biāo)準(zhǔn)包裝: 98
放大器類型: J-FET
電路數(shù): 1
轉(zhuǎn)換速率: 60 V/µs
增益帶寬積: 25MHz
電流 - 輸入偏壓: 3pA
電壓 - 輸入偏移: 85µV
電流 - 電源: 3mA
電流 - 輸出 / 通道: 45mA
電壓 - 電源,單路/雙路(±): ±5 V ~ 13 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
產(chǎn)品目錄頁面: 773 (CN2011-ZH PDF)
AD8610/AD8620
Rev. F | Page 15 of 24
Slew Rate (Unity Gain Inverting vs. Noninverting)
Amplifiers generally have a faster slew rate in an inverting unity
gain configuration due to the absence of the differential input
capacitance. Figure 49 through Figure 52 show the performance
of the AD8610/AD8620 configured in a unity gain of –1 compared
to the OPA627. The AD8610/AD8620 slew rate is more symme-
trical, and both the positive and negative transitions are much
cleaner than in the OPA627.
02
73
0-
0
49
V
O
L
T
A
G
E
(
5V/
D
IV)
TIME (400ns/DIV)
VS = ±13V
RL = 2k
G= –1
SR = 54V/s
Figure 49. +Slew Rate of AD8610/AD8620 in Unity Gain of –1
02
73
0-
0
50
VO
L
T
A
G
E
(
5V/
D
IV)
TIME (400ns/DIV)
VS = ±13V
RL = 2k
G= –1
SR = 42.1V/s
Figure 50. +Slew Rate of OPA627 in Unity Gain of –1
02
730
-05
1
VO
L
T
A
G
E
(
5V/
D
IV
)
TIME (400ns/DIV)
VS = ±13V
RL = 2k
G= –1
SR = 54V/s
Figure 51. –Slew Rate of AD8610/AD8620 in Unity Gain of –1
02
73
0-
0
52
VO
L
T
A
G
E
(
5V/
D
IV)
TIME (400ns/DIV)
VS = ±13V
RL = 2k
G= –1
SR = 56V/s
Figure 52. –Slew Rate of OPA627 in Unity Gain of –1
The AD8610/AD8620 have a very fast slew rate of 60 V/μs even
when configured in a noninverting gain of +1. This is the toughest
condition to impose on any amplifier because the input common-
mode capacitance of the amplifier generally makes its SR appear
worse. The slew rate of an amplifier varies according to the voltage
difference between its two inputs. To observe the maximum SR,
a voltage difference of about 2 V between the inputs must be
ensured. This is required for virtually any JFET op amp so that
one side of the op amp input circuit is completely off, thus maxi-
mizing the current available to charge and discharge the internal
compensation capacitance. Lower differential drive voltages
produce lower slew rate readings. A JFET input op amp with a
slew rate of 60 V/μs at unity gain with VIN = 10 V may slew at
20 V/μs if it is operated at a gain of +100 with VIN = 100 mV.
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