
Data Sheet
AD8605/AD8606/AD8608
Rev. N | Page 21 of 24
OUTLINE DIMENSIONS
02-
15-
2013
-B
A
B
C
0.610
0.555
0.500
0.230
0.200
0.170
0.940
0.900
0.860
1.330
1.290
1.250
1
2
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
SIDE VIEW
0.280
0.260
0.240
0.866
REF
BALL A1
IDENTIFIER
SEATING
PLANE
0.50 BSC
COPLANARITY
0.05
0.50
BSC
Figure 58. 5-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-5-1)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-178-AA
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
5
12
3
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
11-0
1-20
10-A
Figure 59. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters