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參數(shù)資料
| 型號： | AD8564ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | Quad 7 ns Single Supply Comparator |
| 中文描述： | QUAD COMPARATOR, 8000 uV OFFSET-MAX, 8 ns RESPONSE TIME, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 115K |
| 代理商： | AD8564ARU |
AD8564
–
6
–
REV. A
INPUT STAGE AND BIAS CURRENTS
The AD8564 uses a PNP differential input stage which enables
the input common-mode range to extend all the way from the
negative supply rail to within 2.2 V of the positive supply rail.
The input common-mode voltage can be found as the average of
the voltage at the two inputs of the device. To ensure the fastest
response time, care should be taken to not allow the input
common-mode voltage to exceed this voltage.
The input bias current for the AD8564 is 4
μ
A. As with any
PNP differential input stage, this bias current will go to zero on
an input that is high and will double on an input that is low.
Care should be taken in choosing resistor values to be connected
to the inputs as large resistors could cause significant voltage
drops due to the input bias current.
The input capacitance for the AD8564 is typically 3 pF. This is
measured by inserting a k
source resistance to the input and
measuring the change in propagation delay.
USING HYSTERESIS
Hysteresis can easily be added to a comparator through the
addition of positive feedback. Adding hysteresis to a comparator
offers an advantage in noisy environments where it is not desir-
able for the output to toggle between states when the input
signal is near the switching threshold. Figure 14 shows a method
for configuring the AD8564 with hysteresis.
COMPARATOR
SIGNAL
R1
R2
V
REF
C
F
Figure 14. Configuring the AD8564 with Hysteresis
The input signal is connected directly to the inverting input of
the comparator. The output is fed back to the noninverting
input through R2 and R1. The ratio of R1 to R1 + R2 estab-
lishes the width of the hysteresis window with V
REF
setting the
center of the window, or the average switching voltage. The
output will switch high when the input voltage is greater than
V
HI
and will not switch low again until the input voltage is less
than V
LO
as given in Equation 1:
V
HI
=
V
+
–1–
V
REF
(
)
R
1
R
1
+
R
2
+
V
REF
V
LO
=
V
REF
1–
R
1
R
1
+
R
2
(1)
Where
V
+
is the positive supply voltage.
The capacitor C
F
can also be added to introduce a pole into the
feedback network. This has the effect of increasing the amount
of hysteresis at high frequencies. This can be useful when com-
paring a relatively slow signal in a high frequency noise environ-
ment. At frequencies greater than
f
P
=
1
2
π
C
F
R
2
, the hysteresis
window approaches V
HI
= V
+
– 1 V and V
LO
= 0 V. At frequen-
cies less than
f
P
the threshold voltages remain as in Equation 1.
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| AD8564ARU-REEL | 功能描述:IC COMP QUAD 7NS FAST 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| AD8564ARUZ | 制造商:Analog Devices 功能描述: |
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