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參數(shù)資料
| 型號： | AD8527ARMZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP GP R-R 7MHZ DUAL 8MSOP |
| 標準包裝： | 1 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉換速率： | 8 V/µs |
| 增益帶寬積： | 7MHz |
| 電流 - 輸入偏壓： | 450nA |
| 電壓 - 輸入偏移： | 1300µV |
| 電流 - 電源： | 900µA |
| 電流 - 輸出 / 通道： | 10mA |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | AD8527ARMZ-REELDKR |
AD8517/AD8527
–9–
REV. B
Q14
IN
VEE
VCC
VOUT
Q1
Q3
R5
R6
I2
R1
IN
R2
R4
R3
I1
R7
R8
D2
ESD
D7
D8
Q2
Q4
D1
ESD
D3
ESD
D4
ESD
Q5
Q6
Q7
C1
Q8
Q11
Q9
I4
I3
I5
Q13
I7
I6
C3
R10
R9
R11
Q15
Q17
D6
R12
Q18
I8
C2
R14
Q19
Q20
C4
D9
VCC
D16
R13
VEE
Q10
Figure 19. Simplified Schematic
Table I. Typical Battery Life Voltage Range
Nominal
End of Voltage
Battery
Voltage (V)
Discharge (V)
Lead-Acid
2
1.8
Lithium
2.6-3.6
1.7-2.4
NiMH
1.2
1
NiCd
1.2
1
Carbon-Zinc
1.5
1.1
RAIL-TO-RAIL INPUT AND OUTPUT
The AD8517 features an extraordinary rail-to-rail input and
output with supply voltages as low as 1.8 V. With the amplifier’s
supply range set to 1.8 V, the input can be set to 1.8 V p-p,
allowing the output to swing to both rails without clipping. Figure
20 shows a scope picture of both input and output taken at unity
gain, with a frequency of 1 kHz, at VS = 1.8 V and VIN = 1.8 V p-p.
TIME – 200 s/Div
VS = 0.9V
VIN = 1.8 V p-p
VIN
VOUT
Figure 20. Rail-to-Rail Input Output
The rail-to-rail feature of the AD8517 can be observed over the
supply voltage range, 1.8 V to 5 V. Traces are shown offset for
clarity.
INPUT BIAS CONSIDERATION
The input bias current (IB) is a nonideal, real-life parameter that
affects all op amps. IB can generate a somewhat significant offset
voltage. This offset voltage is created by IB when flowing through
the negative feedback resistor RF. If IB is 500 nA (worst case),
and RF is 100 k
, the corresponding generated offset voltage is
50 mV (VOS = IB
RF).
Obviously the lower RF the lower the generated voltage offset.
Using a compensation resistor, RB, as shown in Figure 21, can
significantly minimize this effect. With the input bias current mini-
mized, we still need to be aware of the input offset current (IOS)
which will generate a slight offset error. Figure 21 shows three
different configurations to minimize IB-induced offset errors.
NONINVERTING CONFIGURATION
RB = RI RF
VOUT
RF
RI
VI
AD8517
RS
UNITY GAIN BUFFER
VOUT
RF = RS
VI
AD8517
VOUT
RF
RI
RB = RI RF
VI
INVERTING CONFIGURATION
AD8517
Figure 21. Input Bias Cancellation Circuits
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